3 V/5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Four 8-bit DACs in one package
V
B
V
A
V
REF
REF
DD
+3 V, +5 V, and 5 V operation
8
8
8
8
8
PWR-ON
RESET
INPUT
REG A
DAC A
REG
V
V
V
V
A
B
C
D
DAC A
DAC B
DAC C
DAC D
Rail-to-rail REF input to voltage output swing
2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown
OUT
8
8
8
8
INPUT
REG B
DAC B
REG
OUT
CS
INPUT
REG C
DAC C
REG
OUT
OUT
SERIAL
REG
SDI/SHDN
CLK
INPUT
REG D
DAC D
REG
APPLICATIONS
Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when VDD < 5.5 V
AD7304
V
GND
V
C V
D
REF
SS
REF
CLR LDAC
Figure 1.
V
8
V
REF
DD
GENERAL DESCRIPTION
8
PWR-ON
RESET
INPUT
REG A
DAC A
The AD7304/AD73051 are quad, 8-bit DACs that operate from
a single +3 V to +5 V supply, or 5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.
V
V
A
DAC A
DAC B
DAC C
DAC D
OUT
REG
DB0
DB1
DB2
DB3
DB4
DB5
DB6
8
8
8
8
8
INPUT
REG B
DAC B
B
OUT
REG
8
INPUT
REG C
DAC C
V
V
C
D
OUT
OUT
REG
8
8
INPUT
REG D
DAC D
REG
WR
A0/SHDN
A1
DECODE
AD7305
V
SS
GND
LDAC
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail VREF input to
DAC VOUT allows for a full-scale voltage set equal to the positive
supply, VDD, the negative supply, VSS, or any value in between.
Figure 2.
When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.
The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.
CS
using data in (SDI), clock (CLK), and chip select ( ) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
The AD7304/AD7305 are specified over the extended industrial
−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.
WR
along with the
registers.
control line to load data into the input
The double-buffered architecture allows all four input registers
LDAC
to be preloaded with new values, followed by an
control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.
_____________________________________________________
1 Protected under Patent No. 5684481.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
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