Datasheet > AD7170

AD7170

更新时间： 2022-12-26 19:16:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	266K
描述
12-Bit Low Power Sigma-Delta ADC

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AD7170 数据手册

AD7170

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V_DD, unless otherwise noted.

Table 2.

Parameter^{1, 2}

Limit at T_MIN, T_MAX

Unit

Conditions/Comments

READ

t₁

t₂

t₃

100

ns min

ns max

ns min

SCLK high pulse width

SCLK low pulse width

SCLK active edge to data valid delay⁴

V_DD= 4.75 V to 5.25 V

V_DD= 2.7 V to 3.6 V

t₄

SCLK inactive edge to DOUT/RDY high

RESET

t₅

t₆

100

ns min

ms typ

PDRST low pulse width

PDRST high to data valid delay

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

²See Figure 3.

³These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴SCLK active edge is the falling edge of SCLK.

(1.6mA WITH V = 5V,

SINK

100µA WITH V = 3V)

OUTPUT

1.6V

50pF

(200µA WITH V = 5V,

SOURCE

100µA WITH V = 3V)

Figure 2. Load Circuit for Timing Characterization

TIMING DIAGRAMS

MSB

t₃

LSB

t₄

DOUT/RDY (O)

t₁

SCLK (I)

t₂

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

PDRST (I)

t₅

t₆

DOUT/RDY (O)

I = INPUT, O = OUTPUT

Figure 4. Resetting the AD7170

Rev. 0 | Page 5 of 16

1 2 3 456 7 8...16

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