Datasheet > AD7170

AD7170

更新时间： 2022-12-26 19:16:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	266K
描述
12-Bit Low Power Sigma-Delta ADC

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AD7170 数据手册

AD7170

SPECIFICATIONS

V_DD= 2.7 V to 5.25 V, V_REF= V_DD, GND = 0 V, all specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

AD7170B¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL

Output Data Rate (f_ADC

No Missing Codes²

Noise Free Resolution

Resolution Peak-to-Peak (p-p)

Effective Resolution (ENOB)

RMS Noise

)

125

Bits

μV

LSB

Settling time = 3/f_ADC

V_INx= 0 V, V_REF= V_DD

See Table 6

0.1

Integral Nonlinearity

Offset Error

200

μV

Offset Error Drift vs. Temperature

Full-Scale Error

Gain Drift vs. Temperature

Power Supply Rejection

ANALOG INPUTS

250

nV/°C

% of FS

LSB/°C

0.015

0.07

V_INx= 1 V

Differential Input Voltage Range

Absolute AINx Voltage Limits²

Average Input Current²

V_REF

400

nA/V

V_REF= REFIN(+) − REFIN(−)

GND − 0.03

V_DD+ 0.03

Input current varies with input

voltage

Average Input Current Drift

DC Common-Mode Rejection

REFERENCE

pA/V/°C

V_INx= 1 V

External REFIN Voltage

V_DD

REFIN = REFIN(+) − REFIN(−)

Reference Voltage Range²

Absolute REFIN Voltage Limits²

Average Reference Input Current

Drift

0.5

GND − 0.03

V_DD

V_DD+ 0.03

400

0.15

nA/V

nA/V/°C

DC Common-Mode Rejection

INTERNAL CLOCK

Frequency²

110

64 − 5%

64 + 5%

kHz

LOGIC INPUTS

SCLK, PDRST²

Input Low Voltage, V_INL

0.4

0.8

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

Input High Voltage, V_INH

1.8

2.4

SCLK (Schmitt-Triggered Input)²

Hysteresis

100

140

ꢀA

V_DD= 3 V

V_DD= 5 V

V_IN= V_DDor GND

All digital inputs

Input Currents

Input Capacitance

Rev. 0 | Page 3 of 16

1 234 5 6 7...16

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