AD6643BCPZRL7-200

更新时间： 2024-01-01 17:20:22

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
36页	1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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中文翻译

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数据手册
替代型号

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AD6643BCPZRL7-200 数据手册

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AD6643

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 14 are not currently supported for this device.

Table 14. Memory Map Registers

Default

Value

(Hex)

Addr Register

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Default Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

0x00

SPI port

LSB

first

Soft reset

LSB first

0x18

The nibbles

configuration

are mirrored so

LSB-first mode or

MSB-first mode

registers correctly,

regardless of shift

mode

(global)¹

0x01

0x02

Chip ID

(global)

8-Bit Chip ID[7:0]

(AD6643 = 0x84)

(default)

0x84

Read only

Chip grade

(global)

Open

Speed grade ID

10 = 200 MSPS

Open Open

Open

Speed grade ID

used to

differentiate

devices; read

only

Channel Index and Transfer Registers

0x0ꢀ

Channel

index

(global)

Open

Open Open

Open

Open Open

ADC B

(default)

ADC A

(default)

0x03

Bits are set

to determine

which device on

the chip receives

the next write

command;

applies to local

registers only

0xFF

Transfer

(global)

Open

Open Open

Open

Open Open

Open

Transfer

0x00

Synchronously

transfers data

from the master

shift register to

the slave

ADC Functions

0x08

Power

modes (local)

Open External

power-

Internal power-down

mode (local)

00 = normal operation

01 = full power-down

10 = standby

Determines

various generic

modes of chip

operation

down pin

function

(local)

11 = reserved

0 = power-

down

1 = standby

0x09

0x0B

Global clock

(global)

Open

Open Open

Open

Open Open

Open

Duty cycle 0x01

stabilizer

(default)

Clock divide

(global)

Open

Input clock divider

phase adjust

000 = no delay

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by ꢀ

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

Clock divide

values other

than 000 auto-

matically cause

the duty cycle

stabilizer to

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = ꢀ input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

become active

Rev. 0 | Page 30 of 36

1...27 28 293031 32 33...36

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AD6643BCPZRL7-200 替代型号

型号	品牌	替代类型	描述	数据表
AD6643BCPZ-200	ADI	完全替代	Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

与AD6643BCPZRL7-200相关器件

型号	品牌	获取价格	描述	数据表
AD6643BCPZRL7-250	ADI	获取价格	Dual IF Receiver
AD6644	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644_17	ADI	获取价格	Analog-to-Digital Converter
AD6644AST-40	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644AST-65	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644ASTZ-40	ADI	获取价格	Analog-to-Digital Converter
AD6644ASTZ-65	ROCHESTER	获取价格	1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, LOW PROFILE, PLASTIC, MS-026B
AD6644ASTZ-65	ADI	获取价格	Analog-to-Digital Converter
AD6644PCB	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644ST	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter

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