AD6643BCPZRL7-200

更新时间： 2024-02-18 04:50:20

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
36页	1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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AD6643BCPZRL7-200 数据手册

AD6643

NSR Control (Register 0x3C)

Bits[7:4]—Reserved

SYNC Pin Control (Register 0x59)

Bits[7:2]—Reserved

Bits[3:1]—NSR Mode

Bit 1—SYNC Pin Sensitivity

Bits[3:1] determine the bandwidth mode of the NSR. When

Bits[3:1] are set to 000, the NSR is configured for a 22% BW

mode that provides enhanced SNR performance over 22% of

the sample rate. When Bits[3:1] are set to 001, the NSR is con-

figured for a 33% BW mode that provides enhanced SNR

performance over 33% of the sample rate.

If Bit 1 is set to a 0, the SYNC input responds to a level. If this

bit is set to high, the SYNC input responds to the edge (rising or

falling) set in Bit 0 of Address 0x59.

Bit 0—SYNC Pin Edge Sensitivity

If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to

respond to a falling edge. Likewise, if Bit 0 is set to 1, the SYNC

input responds to a rising edge.

Bit 0—NSR Enable

The NSR is enabled when Bit 0 is high and disabled when Bit 0

is low.

NSR Tuning Word (Register 0x3E)

Bits[7:6]—Reserved

Bits[5:0]—NSR Tuning Word

The NSR tuning word sets the band edges of the NSR band. In

22% BW mode, there are 57 possible tuning words; in 33% BW

mode, there are 34 possible tuning words. For either mode, each

step represents 0.5% of the ADC sample rate. For the equations

that are used to calculate the tuning word based on the BW

mode of operation, see the Noise Shaping Requantizer (NSR)

section.

Rev. 0 | Page 33 of 36

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