2 Pair/1 Pair ETSI Compatible
HDSL Analog Front End
a
AD6472
FEATURES
GENERAL D ESCRIP TIO N
Integrated Front End for Single Pair or Tw o Pair HDSL
System s
Meets ETSI Specifications
T he AD6472 is a single chip analog front end for two pair or
single pair HDSL applications that use 1168 Kbps or 2.32 Mbps
data rates.
Supports 1168 Kbps and 2.32 Mbps
Transm it and Receive Signal Path Functions
Receive Hybrid Am plifier, PGA and ADC
Transm it DAC, Filter and Differential Outputs
Program m able Filters
T he AD6472 integrates all the transmit and receive functional
blocks together with the timing recovery DAC.
T he digital interface is designed to support industry standard
digital transceivers.
Control and Ancillary Functions
Tim ing Recovery DAC
Norm al Loopback and Low Pow er Modes
Sim ple Interface-to-Digital Transceivers
Single 5 V Pow er Supply
Pow er Consum ption: 320 m W—(Excluding Driver)
Package: 80-Lead MQFP
Operating Tem perature: –40؇C to +85؇C
While providing the full analog front end for ET SI standards
(two pair or single pair HDSL applications) the AD6472 sup-
ports other applications because the architecture allows for
bypassing the functional blocks.
T he normal, low power, and loopback modes and the digital
interface combine to make the AD6472 simple to integrate into
systems.
FUNCTIO NAL BLO CK D IAGRAM
TX_GAIN
DRIVER
2
12-BIT
DAC
2
ANALOG
FILTER
T
X
2
2
7-BIT
DAC
TO
VCXO
AD6472
CONTROL
LOGIC
BUFFER
2
2
2
2
12-BIT
ADC
ANALOG
FILTER
HYBRID
CIRCUIT
R
PGA
3
X
2
REV. 0
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reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 1998