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AD6472BS PDF预览

AD6472BS

更新时间: 2024-01-09 23:25:49
品牌 Logo 应用领域
亚德诺 - ADI 数字传输接口电信集成电路电信电路
页数 文件大小 规格书
8页 114K
描述
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End

AD6472BS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, MQFP-80
针数:80Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.88Is Samacsys:N
数据速率:2320 MbpsJESD-30 代码:S-PQFP-G80
JESD-609代码:e0长度:14 mm
功能数量:1端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP80,.68SQ封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):220
电源:3.3,5 V认证状态:Not Qualified
座面最大高度:3.4 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:DIGITAL SLIC温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

AD6472BS 数据手册

 浏览型号AD6472BS的Datasheet PDF文件第2页浏览型号AD6472BS的Datasheet PDF文件第3页浏览型号AD6472BS的Datasheet PDF文件第4页浏览型号AD6472BS的Datasheet PDF文件第5页浏览型号AD6472BS的Datasheet PDF文件第6页浏览型号AD6472BS的Datasheet PDF文件第7页 
2 Pair/1 Pair ETSI Compatible  
HDSL Analog Front End  
a
AD6472  
FEATURES  
GENERAL D ESCRIP TIO N  
Integrated Front End for Single Pair or Tw o Pair HDSL  
System s  
Meets ETSI Specifications  
T he AD6472 is a single chip analog front end for two pair or  
single pair HDSL applications that use 1168 Kbps or 2.32 Mbps  
data rates.  
Supports 1168 Kbps and 2.32 Mbps  
Transm it and Receive Signal Path Functions  
Receive Hybrid Am plifier, PGA and ADC  
Transm it DAC, Filter and Differential Outputs  
Program m able Filters  
T he AD6472 integrates all the transmit and receive functional  
blocks together with the timing recovery DAC.  
T he digital interface is designed to support industry standard  
digital transceivers.  
Control and Ancillary Functions  
Tim ing Recovery DAC  
Norm al Loopback and Low Pow er Modes  
Sim ple Interface-to-Digital Transceivers  
Single 5 V Pow er Supply  
Pow er Consum ption: 320 m W—(Excluding Driver)  
Package: 80-Lead MQFP  
Operating Tem perature: 40؇C to +85؇C  
While providing the full analog front end for ET SI standards  
(two pair or single pair HDSL applications) the AD6472 sup-  
ports other applications because the architecture allows for  
bypassing the functional blocks.  
T he normal, low power, and loopback modes and the digital  
interface combine to make the AD6472 simple to integrate into  
systems.  
FUNCTIO NAL BLO CK D IAGRAM  
TX_GAIN  
DRIVER  
2
12-BIT  
DAC  
2
ANALOG  
FILTER  
T
X
2
2
7-BIT  
DAC  
TO  
VCXO  
AD6472  
CONTROL  
LOGIC  
BUFFER  
2
2
2
2
12-BIT  
ADC  
ANALOG  
FILTER  
HYBRID  
CIRCUIT  
R
PGA  
3
X
2
REV. 0  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781/ 329-4700  
Fax: 781/ 326-8703  
World Wide Web Site: http:/ / w w w .analog.com  
© Analog Devices, Inc., 1998  

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