AD6472
P IN CO NFIGURATIO NS
P in Mnem onic
P in Mnem onic
D escription
D escription
1
+5 V_DVDD
DGND
+5 V Digital Supply.
41
42
43
44
45
46
47
HYB_IN1_A
AGND
Hybrid Inverting Input.
Analog Ground.
2
Digital Ground.
3
MODE_SEL0
MODE_SEL1
AA_FLT R_BP
PWRDN
Bit Rate—Filter Corner Select.
Bit Rate—Filter Corner Select.
Antialiasing Filter Bypass.
Power-Down Active Low.
No Connect.
AVDD
+5 V Analog Supply.
PGA Gain Select Bits.
PGA Gain Select Bits.
PGA Gain Select Bits.
4
PGA_GC2
PGA_GC1
PGA_GC0
5
6
7
NC
AA_FLT R_OUT B Differential Output of the
Antialiasing Filter.
8
T X_GAIN_SEL
T X_DRVR_BP
ADC_BUF_BP
T X_LPF_BP
T ST GND
T ransmit Attenuation (6 dB) Select.
T ransmit Driver Bypass.
ADC Buffer Bypass.
48
AA_FLT R_OUT A Differential Output of the
Antialiasing Filter.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
49
50
51
52
53
54
55
ADC_INB
ADC_INA
REF_COM
CAP_T OP
CAP_BOT
VREF
Differential Input to the ADC.
Differential Input to the ADC.
Reference Common.
T ransmit Filter Bypass.
Factory test pin. Connect to DGND.
Loopback Select.
LOOPBACK
DGND
Decoupling Pin for ADC Reference.
Decoupling Pin for ADC Reference.
External Voltage Reference.
Digital Ground.
+3 V_DVDD
T X_DAT A
T X_SYNC
T X_CLK
+3.3 V Digital Supply.
T ransmit Data Input.
T ransmit Data Frame Sync Input.
T ransmit Clock Input.
+5 V Digital Supply.
CM_LVL
Common-Mode Level.
(1/2 Supply Voltage, Nominally.)
56
57
58
59
60
61
62
AGND
Analog Ground.
+5 V_DVDD
DGND
AVDD
+5 V Analog Supply.
Digital Ground.
Digital Ground.
DGND
NC
No Connect.
+5 V_ DVDD
NC
+5 V Digital Supply.
No Connect.
IOUT _SET
DAC Output Current Full Scale
(With Resistor to Ground).
+3 V_ DVDD
T R_DAC_OUT
+3 V Digital Supply.
23
24
25
26
NC
No Connect.
T iming Recovery DAC Output
Voltage.
CAP_B
CAP_C
T X_IOUT _A
Decoupling Pin for Internal Node.
Decoupling Pin for Internal Node.
63
SDAT A
Serial Data Input to T iming Recov-
ery DAC.
T XDAC Complementary Current
Output.
64
65
SFRAME
SCLK
Frame Sync for T iming Recovery.
27
T X_IOUT _B
T XDAC Complementary Current
Output.
Clock for T iming Recovery DAC.
Serial Data.
28
29
30
31
32
AGND
Analog Ground.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RX0
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Ground.
AVDD
+5 V Analog Supply.
Differential Input to LPF.
Differential Input to LPF.
RX1
T X_LPF_IN_B
T X_LPF_IN_A
RX2
RX3
T X_LPF_OUT _B Differential Output from T ransmit
(If Driver Bypassed).
RX4
RX5
33
T X_LPF_OUT _A Differential Output from T ransmit
(If Driver Bypassed).
DGND
+3 V_DVDD
RX6
+3 V Digital Supply.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Digital Output Data.
Clock Input for ADC Data.
34
35
36
37
38
39
40
AVDD
+5 V Analog Supply.
DRVR_OUT _B
DRVR_OUT _A
AGND
Differential Driver Output.
Differential Driver Output.
Analog Ground.
RX7
RX8
RX9
HYB_IN2_B
HYB_IN2_A
HYB_IN1_B
Hybrid Noninverting Input.
Hybrid Noninverting Input.
Hybrid Inverting Input.
RX10
RX11
RXCLK
–4–
REV. 0