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AD5732BREZ-REEL7 PDF预览

AD5732BREZ-REEL7

更新时间: 2024-09-18 03:13:23
品牌 Logo 应用领域
亚德诺 - ADI 输入元件光电二极管
页数 文件大小 规格书
32页 1163K
描述
IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO24, LEAD FREE, MO-153ADT, TSSOP-24, Digital to Analog Converter

AD5732BREZ-REEL7 数据手册

 浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第3页浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第4页浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第5页浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第7页浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第8页浏览型号AD5732BREZ-REEL7的Datasheet PDF文件第9页 
AD5722/AD5732/AD5752  
Preliminary Technical Data  
SINGLE SUPPLY SPECIFICATIONS  
AVDD = 4.5 V1 to 16.5 V, AVꢀꢀ = 0 V, GND = 0 V, REFIN = 2.5 V, DVCC = 2.7 V to 5.5 V  
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, 10 V range unless otherwise noted.  
Table 3.  
Parameter  
Value  
Unit  
Test Conditions/Comments  
Outputs unloaded  
ACCURACY  
Resolution  
AD5752  
AD5732  
AD5722  
Total Unadjusted Error (TUE)  
Relative Accuracy (INL)  
B Grade  
Differential Nonlinearity (DNL)  
Zero-Scale Error  
Zero-Scale TC2  
16  
14  
12  
0.1  
Bits  
Bits  
Bits  
% FSR max  
Across temperature and supplies  
±16  
±1  
+10  
±4  
±10  
±0.02  
±±  
LSB max  
LSB max  
mV max  
ppm FSR/°C max  
mV max  
% FSR max  
ppm FSR/°C max  
LSB max  
@ 16-bit resolution  
Guaranteed monotonic (@ 16-bit resolution)  
@ 25°C, error at other temperatures obtained using Zero-Scale TC  
Offset Error  
Gain Error  
@ 25°C, error at other temperatures obtained using Gain TC  
@ 16-bit resolution  
Gain TC2  
DC Crosstalk2  
0.6  
REFERENCE INPUT 2  
Reference Input Voltage  
DC Input Impedance  
Input Current  
Reference Range  
OUTPUT CHARACTERISTICS2  
Output Voltage Range  
2.5  
1
±10  
2 to 3  
V nom  
MΩ min  
µA max  
V min to V max  
±1% for specified performance  
Typically 100 MΩ  
Typically ±30 nA  
10.±  
12  
V max  
V max  
AVDD = 11.7 V min, REFIN = 2.5 V  
AVDD = 12.ꢀ V min, REFIN = 3.75 V  
Headroom  
0.ꢀ  
0.5  
±±  
±12  
±15  
20  
V max  
V typ  
ppm FSR/°C max  
ppm/500 hr typ  
ppm/1000 hr typ  
mA max  
Output Voltage TC  
Output Voltage Drift vs. Time  
Short Circuit Current  
Load  
2
KΩ max  
For specified performance  
Capacitive Load Stability  
DC Output Impedance  
DIGITAL INPUTS2  
4000  
0.5  
pF max  
Ω typ  
DVCC = 2.7 V to 5.5 V, JEDEC compliant  
VIH, Input High Voltage  
VIL, Input Low Voltage  
Input Current  
2
V min  
0.±  
±1  
5
V max  
µA max  
pF max  
Per pin  
Per pin  
Pin Capacitance  
DIGITAL OUTPUTS (SDO)2  
VOL, Output Low Voltage  
VOH, Output High Voltage  
VOL, Output Low Voltage  
VOH, Output High Voltage  
High Impedance Leakage Current  
High Impedance Output Capacitance  
POWER REQUIREMENTS  
AVDD  
0.4  
DVCC − 1  
0.4  
DVCC − 0.5  
±1  
5
V max  
V min  
V max  
V min  
µA max  
pF typ  
DVCC = 5 V ± 10%, sinking 200 µA  
DVCC = 5 V ± 10%, sourcing 200 µA  
DVCC = 2.7 V to 3.6 V, sinking 200 µA  
DVCC = 2.7 V to 3.6 V, sourcing 200 µA  
4.5 to 16.5  
2.7 to 5.5  
V min to V max  
V min to V max  
DVCC  
Power Supply Sensitivity2  
Rev. PrC | Page 6 of 32  

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