Octal, 16-Bit nanoDAC+ with SPI Interface
Data Sheet
AD5676
FEATURES
GENERAL DESCRIPTION
High performance
The AD5676 is a low power, octal, 16-bit buffered voltage
High relative accuracy (INL): 3 LSB maximum at 16 bits
Total unadjusted error (TUE): 0.14% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.06% of FSR maximum
Wide operating ranges
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP and LFCSP RoHS-compliant packages
Table 1. Octal nanoDAC+® Devices
APPLICATIONS
Interface
Reference
Internal
External
Internal
External
16-Bit
12-Bit
Optical transceivers
SPI
AD5676R
AD5676
AD5675R
AD5675
AD5672R
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Not applicable
AD5671R
I2C
Not applicable
Data acquisition systems
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: 3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REF
LOGIC
DD
AD5676
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
DAC
STRING
DAC 0
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
SCLK
SYNC
SDI
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 3
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 4
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
LDAC
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
POWER-DOWN
LOGIC
POWER-ON RESET
GAIN x1/x2
GAIN
RSTSEL
GND
Figure 1.
Rev. B
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