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AD5675RACPZ-REEL7

更新时间： 2024-11-28 00:56:27
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亚德诺 - ADI /
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32页 841K
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Base station power amplifiers

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AD5675RACPZ-REEL7 数据手册

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Octal, 12-/16-Bit nanoDAC+ with  
2 ppm/°C Reference, I2C Interface  
AD5671R/AD5675R  
Data Sheet  
FEATURES  
GENERAL DESCRIPTION  
The AD5671R/AD5675R are low power, octal, 12-/16-bit  
buffered voltage output digital-to-analog converters (DACs).  
They include a 2.5 V, 2 ppm/°C internal reference (enabled by  
default) and a gain select pin giving a full-scale output of 2.5 V  
(gain = 1) or 5 V (gain = 2). The devices operate from a single  
2.7 V to 5.5 V supply and are guaranteed monotonic by design.  
The AD5671R/AD5675R are available in a 20-lead TSSOP and in  
a 20-lead LFCSP and incorporate a power-on reset circuit and a  
RSTSEL pin that ensures the DAC outputs power up to zero scale  
or midscale and remain there until a valid write. The AD5671R/  
AD5675R contain a power-down mode, reducing the current  
consumption to 1 μA typical while in power-down mode.  
High performance  
High relative accuracy (INL): 3 LSB maximum at 16 bits  
Total unadjusted error (TUE): 0.14ꢀ of FSR maximum  
Offset error: 1.5 mꢁ maximum  
Gain error: 0.06ꢀ of FSR maximum  
Low drift 2.5 ꢁ reference: 2 ppm/°C typical  
Wide operating ranges  
−40°C to +125°C temperature range  
2.7 ꢁ to 5.5 ꢁ power supply  
Easy implementation  
User selectable gain of 1 or 2 (GAIN pin/bit)  
1.8 ꢁ logic compatibility  
400 kHz I2C-compatible serial interface  
Robust 2 kꢁ HBM and 1.5 kꢁ FICDM ESD rating  
20-lead, RoHS-compliant TSSOP and LFCSP  
Table 1. Octal nanoDAC+® Devices  
Interface  
Reference  
16-Bit  
12-Bit  
SPI  
Internal  
External  
Internal  
AD5676R  
AD5676  
AD5675R  
AD5672R  
Not applicable  
AD5671R  
APPLICATIONS  
Optical transceivers  
I2C  
Base station power amplifiers  
Process control (PLC input/output cards)  
Industrial automation  
PRODUCT HIGHLIGHTS  
1. High Relative Accuracy (INL)  
AD5671R (12-bit): ±1 LSB maximum  
AD5675R (16-bit): ±± LSB maximum  
2. Low Drift, 2.5 V On-Chip Reference  
Data acquisition systems  
FUNCTIONAL BLOCK DIAGRAM  
V
V
V
REFOUT  
LOGIC  
DD  
AD5671R/AD5675R  
2.5V  
REF  
BUFFER  
BUFFER  
BUFFER  
BUFFER  
BUFFER  
BUFFER  
BUFFER  
BUFFER  
DAC  
STRING  
DAC 0  
INPUT  
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
REGISTER  
REGISTER  
DAC  
REGISTER  
STRING  
DAC 1  
INPUT  
REGISTER  
DAC  
REGISTER  
STRING  
DAC 2  
INPUT  
REGISTER  
SCL  
DAC  
REGISTER  
STRING  
DAC 3  
INPUT  
REGISTER  
SDA  
A1  
DAC  
REGISTER  
STRING  
DAC 4  
INPUT  
REGISTER  
DAC  
REGISTER  
STRING  
DAC 5  
INPUT  
REGISTER  
A0  
DAC  
REGISTER  
STRING  
DAC 6  
INPUT  
REGISTER  
LDAC  
DAC  
REGISTER  
STRING  
DAC 7  
INPUT  
REGISTER  
RESET  
GAIN POWER-DOWN  
POWER-ON  
RESET  
×1/×2  
LOGIC  
RSTSEL  
GAIN  
GND  
Figure 1.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
 
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