AD5621AKSZ-REEL7

更新时间： 2024-02-03 11:47:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	466K
描述
2.7 V to 5.5 V, <100 Î¼A, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70

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AD5621AKSZ-REEL7 数据手册

AD5601/AD5611/AD5621

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5601/

AD5611/

OUT

SYNC

SCLK

SDIN

OUT

AD5601/

AD5611/

AD5621

TOP VIEW

(Not to Scale)

SCLK

SDIN

GND

AD5621

GND

TOP VIEW

(Not to Scale)

SYNC

NOTES:

1. CONNECT THE EXPOSED PAD TO GND.

Figure 3. 6-Lead SC70 Pin Configuration

Figure 4. 6-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

SC70 LFCSP

Pin No. Pin No.

Mnemonic

Description

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input

data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling

edges of the clocks that follow. The DAC is updated following the 16^thclock cycle, unless SYNC is

taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write

sequence is ignored by the DAC.

SCLK

SDIN

V_DD

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz.

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. V_DDshould be

decoupled to GND.

GND

V_OUT

Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

Exposed Pad. Connect to GND.

Rev. G | Page 6 of 24

1...3 4 567 8 9...24

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