AD5621AKSZ-REEL7

更新时间： 2024-01-15 09:37:27

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	466K
描述
2.7 V to 5.5 V, <100 Î¼A, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70

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AD5621AKSZ-REEL7 数据手册

AD5601/AD5611/AD5621

Data Sheet

A Grade

Min Typ

B Grade

Min Typ

Parameter

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

V_DD

2.7

5.5

2.7

5.5

All digital inputs at 0 V or V_DD

I_DDfor Normal Mode

DAC active and excluding load

current

V_DD

4.5 V to 5.5 V

2.7 V to 3.6 V

100

µA

V_IH= V_DDand V_IL= GND

I_DDfor All Power-Down Modes

V_DD

4.5 V to 5.5 V

2.7 V to 3.6 V

0.5

0.2

0.5

0.2

µA

POWER EFFICIENCY

I_OUT/I_DD

I_LOAD= 2 mA and V_DD= 5 V

¹Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.

²Guaranteed by design and characterization, not production tested.

³Total current flowing into all pins.

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted. See Figure 2.

Table 3.

Parameter

Limit¹

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

t₁

ns min

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

4.5

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK falling edge ignored

¹All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 30 MHz.

t₄

t₂

t₁

t₉

SCLK

SYNC

t₈

t₃

t₇

t₆

t₅

D15

D14

D15

D14

SDIN

Figure 2. Timing Diagram

Rev. G | Page 4 of 24

1 2 345 6 7...24

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