5秒后页面跳转
捷配首页

Datasheet > AD5533ABCZ-1
AD5533ABCZ-1 PDF预览

AD5533ABCZ-1

更新时间： 2024-01-19 00:24:30
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
16页 312K
描述
IC SAMPLE AND HOLD AMPLIFIER, PBGA74, 12 X 12 MM, LFBGA-74, Sample and Hold Circuit

阅读下载

中文翻译

获取价格

AD5533ABCZ-1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：74
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.35
最长采集时间：16 µs放大器类型：SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：3 V最小模拟输入电压：
JESD-30 代码：S-PBGA-B74JESD-609代码：e1
长度：12 mm湿度敏感等级：3
功能数量：1端子数量：74
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
采样并保持/跟踪并保持：SAMPLE座面最大高度：1.7 mm
供电电压上限：7 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
Base Number Matches：1

AD5533ABCZ-1 数据手册

 浏览型号AD5533ABCZ-1的Datasheet PDF文件第10页浏览型号AD5533ABCZ-1的Datasheet PDF文件第11页浏览型号AD5533ABCZ-1的Datasheet PDF文件第12页浏览型号AD5533ABCZ-1的Datasheet PDF文件第13页浏览型号AD5533ABCZ-1的Datasheet PDF文件第15页浏览型号AD5533ABCZ-1的Datasheet PDF文件第16页 
AD5533  
MICROPROCESSOR INTERFACING  
AD5533 to ADSP-21xx Interface  
The ADSP-21xx family of DSPs are easily interfaced to the  
AD5533 without the need for extra logic.  
SPDR Register. PC7 must be pulled low to start a transfer. It is  
taken high and pulled low again before any further read/write cycles  
can take place. A connection diagram is shown in Figure 10.  
AD5533  
*
MC68HC11*  
A data transfer is initiated by writing a word to the Tx Register  
after the SPORT has been enabled. In a write sequence, data is  
clocked out on each rising edge of the DSP’s serial clock and  
clocked into the AD5533 on the falling edge of its SCLK. In  
read back, 16 bits of data are clocked out of the AD5533 on each  
rising edge of SCLK and clocked into the DSP on the rising edge of  
SCLK. DIN is ignored. The valid 14 bits of data will be centered  
in the 16-bit Rx Register when using this configuration. The  
SPORT Control Register should be set up as follows:  
MISO  
PC7  
D
OUT  
SYNC  
SCK  
MOSI  
SCLK  
D
IN  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 10. AD5533 to MC68HC11 Interface  
AD5533 to PIC16C6x/PIC16C7x  
The PIC16C6x Synchronous Serial Port (SSP) is configured as an  
SPI Master with the Clock Polarity Bit = 0. This is done by writing  
to the Synchronous Serial Port Control Register (SSPCON). See  
PIC16/PIC17 Microcontroller User Manual. In this example, I/O port  
RA1 is being used to pulse SYNC and enable the serial port of  
the AD5533. This microcontroller transfers only eight bits of data  
during each serial transfer operation; therefore, two consecutive  
read/write operations are needed for a 10-bit write and a 14-bit  
read back. Figure 11 shows the connection diagram.  
TFSW = RFSW = 1, Alternate Framing  
INVRFS = INVTFS = 1, Active Low Frame Signal  
DTYPE = 00, Right Justify Data  
ISCLK = 1, Internal Serial Clock  
TFSR  
IRFS  
ITFS  
= RFSR = 1, Frame Every Word  
= 0, External Framing Signal  
= 1, Internal Framing Signal  
SLEN = 1001, 10-Bit Data-Words (ISHA Mode Write)  
SLEN = 1111, 16-Bit Data-Words (Readback Mode)  
PIC16C6x/7x*  
AD5533  
*
Figure 9 shows the connection diagram.  
SCK/RC3  
SCLK  
ADSP-2101/  
ADSP-2103*  
AD5533  
*
SDO/RC5  
SDI/RC4  
RA1  
D
OUT  
DR  
D
OUT  
D
IN  
TFS  
RFS  
DT  
SYNC  
SYNC  
*ADDITIONAL PINS OMITTED FOR CLARITY  
D
IN  
SCLK  
Figure 11. AD5533 to PIC16C6x/7x Interface  
AD5533 to 8051  
SCLK  
*ADDITIONAL PINS OMITTED FOR CLARITY  
The AD5533 requires a clock synchronized to the serial data.  
The 8051 serial interface must therefore be operated in Mode 0.  
In this mode, serial data enters and exits through RxD and a  
shift clock is output on TxD. Figure 12 shows how the 8051 is  
connected to the AD5533. Because the AD5533 shifts data  
out on the rising edge of the shift clock and latches data in on  
the falling edge, the shift clock must be inverted. The AD5533  
requires its data with the MSB first. Since the 8051 outputs  
the LSB first, the transmit routine must take this into account.  
Figure 9. AD5533 to ADSP-2101/ADSP-2103 Interface  
AD5533 to MC68HC11  
The Serial Peripheral Interface (SPI) on the MC68HC11 is  
configured for Master Mode (MSTR) = 1, Clock Polarity Bit  
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is  
configured by writing to the SPI Control Register (SPCR)—see  
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of  
the AD5533, the MOSI output drives the serial data line (DIN)  
of the AD5533, and the MISO input is driven from DOUT. The  
SYNC signal is derived from a port line (PC7). When data is  
being transmitted to the AD5533, the SYNC line is taken low  
(PC7). Data appearing on the MOSI output is valid on the falling  
edge of SCK. Serial data from the 68HC11 is transmitted in  
8-bit bytes with only eight falling clock edges occurring in the  
transmit cycle. Data is transmitted MSB first. To transmit 10 data  
bits in ISHA Mode, it is important to left-justify the data in the  
8051*  
AD5533  
*
SCLK  
TxD  
RxD  
D
OUT  
D
IN  
SYNC  
P1.1  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 12. AD5533 to 8051 Interface  
–14–  
REV. A  
 
 
 
 
1...111213141516

中文翻译

下载PDF

AD5533ABCZ-1 替代型号

型号 品牌 替代类型 描述 数据表
AD5533ABC-1REEL ADI

完全替代

 		IC SAMPLE AND HOLD AMPLIFIER, PBGA74, 12 X 12 MM, LFBGA-74, Sample and Hold Circuit

与AD5533ABCZ-1相关器件

型号 品牌 描述 获取价格 数据表
AD5533B ADI 32-Channel Precision Infinite Sample-and-Hold

获取价格
AD5533BBC-1 ADI 32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode

获取价格
AD5535 ADI 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

获取价格
AD5535ABC ADI 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

获取价格
AD5535B ADI 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

获取价格
AD5535BKBC ADI 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

获取价格

与AD5533ABCZ-1相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证