AD5533BBC-1

更新时间： 2024-01-20 21:37:14

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	444K
描述
32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode

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AD5533BBC-1 数据手册

32-Channel, 14-Bit DAC with Precision

Infinite Sample-and-Hold Mode

AD5532B^*

GENERAL DESCRIPTION

FEATURES

The AD5532B is a 32-channel, voltage output, 14-bit DAC with

an additional precision infinite sample-and-hold mode. The

selected DAC register is written to via the 3-wire serial inter-

face and V_OUTfor this DAC is then updated to reflect the new

contents of the DAC register. DAC selection is accomplished via

address bits A0–A4. The output voltage range is determined by

the offset voltage at the OFFS_IN pin and the gain of the

output amplifier. It is restricted to a range from V_SS+ 2 V to

V_DD– 2 V because of the headroom of the output amplifier.

High Integration:

32-Channel DAC in 12 mm ꢀ 12 mm CSPBGA

Guaranteed Monotonic to 14 Bits

Infinite Sample-and-Hold Capability to ꢁ0.018% Accuracy

Infinite Sample-and-Hold Total Unadjusted Error ꢁ2.5 mV

Adjustable Voltage Output Range

Readback Capability

DSP/Microcontroller Compatible Serial Interface

Output Impedance 0.5 ꢂ

Output Voltage Span 10 V

Temperature Range –40ꢃC to +85ꢃC

The device is operated with AV_CC= +5 V 5%, DV_CC= +2.7 V

to +5.25 V, V_SS= –4.75 V to –16.5 V, and V_DD= +8 V to +16.5 V

and requires a stable 3 V reference on REF_IN as well as an

offset voltage on OFFS_IN.

APPLICATIONS

Automatic Test Equipment

Optical Networks

Level Setting

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed

monotonic.

Instrumentation

Industrial Control Systems

Data Acquisition

Low Cost I/O

2. The AD5532B is available in a 74-lead CSPBGA with a body

size of 12 mm ꢀ12 mm.

3. In infinite sample-and-hold mode, a total unadjusted error of

2.5 mV is achieved by laser-trimming on-chip resistors.

FUNCTIONAL BLOCK DIAGRAM

REF IN REF OUT

OFFS IN

AD5532B

OUT

ADC

DAC

TRACK/RESET

BUSY

14-BIT

BUS

OUT

MUX

DAC

DAC GND

AGND

OFFS OUT

DGND

MODE

INTERFACE

CONTROL

LOGIC

SER/PAR

ADDRESS INPUT REGISTER

SCLK

A4–A0

CAL OFFSET_SEL

SYNC/CS

OUT

*Protected by U.S. Patent No. 5,969,657; other patents pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

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