5秒后页面跳转
AD5336 PDF预览

AD5336

更新时间: 2024-01-30 15:21:00
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 352K
描述
2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

AD5336 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-28针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
最大模拟输出电压:2.999 V最小模拟输出电压:0.001 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, 8 BITSJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:9.7 mm
最大线性误差 (EL):0.3906%湿度敏感等级:1
位数:10功能数量:4
端子数量:24最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/5.5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大稳定时间:9 µs标称安定时间 (tstl):7 µs
子类别:Other Converters最大压摆率:0.9 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm

AD5336 数据手册

 浏览型号AD5336的Datasheet PDF文件第6页浏览型号AD5336的Datasheet PDF文件第7页浏览型号AD5336的Datasheet PDF文件第8页浏览型号AD5336的Datasheet PDF文件第10页浏览型号AD5336的Datasheet PDF文件第11页浏览型号AD5336的Datasheet PDF文件第12页 
AD5330/AD5331/AD5340/AD5341  
TERMINOLOGY  
RELATIVE ACCURACY  
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)  
is a measure of the maximum deviation, in LSBs, from a straight  
line passing through the actual endpoints of the DAC transfer  
function. Typical INL versus Code plot can be seen in Figures  
5, 6, and 7.  
GAIN ERROR  
AND  
OFFSET ERROR  
OUTPUT  
VOLTAGE  
ACTUAL  
DIFFERENTIAL NONLINEARITY  
Differential Nonlinearity (DNL) is the difference between the  
measured change and the ideal 1 LSB change between any two  
adjacent codes. A specified differential nonlinearity of 1 LSB  
maximum ensures monotonicity. This DAC is guaranteed mono-  
tonic by design. Typical DNL versus Code plot can be seen in  
Figures 8, 9, and 10.  
IDEAL  
POSITIVE  
OFFSET  
DAC CODE  
GAIN ERROR  
This is a measure of the span error of the DAC (including any  
error in the gain of the buffer amplifier). It is the deviation in  
slope of the actual DAC transfer characteristic from the ideal  
expressed as a percentage of the full-scale range. This is illus-  
trated in Figure 2.  
Figure 3. Positive Offset Error and Gain Error  
GAIN ERROR  
AND  
OFFSET ERROR  
OFFSET ERROR  
This is a measure of the offset error of the DAC and the output  
amplifier. It is expressed as a percentage of the full-scale range.  
OUTPUT  
VOLTAGE  
ACTUAL  
IDEAL  
If the offset voltage is positive, the output voltage will still be  
positive at zero input code. This is shown in Figure 3. Because  
the DACs operate from a single supply, a negative offset cannot  
appear at the output of the buffer amplifier. Instead, there will  
be a code close to zero at which the amplifier output saturates  
(amplifier footroom). Below this code there will be a deadband  
over which the output voltage will not change. This is illustrated  
in Figure 4.  
NEGATIVE  
OFFSET  
DAC CODE  
POSITIVE  
GAIN ERROR  
DEADBAND CODES  
AMPLIFIER  
FOOTROOM  
(~1mV)  
NEGATIVE  
GAIN  
ERROR  
OUTPUT  
VOLTAGE  
ACTUAL  
NEGATIVE  
OFFSET  
IDEAL  
Figure 4. Negative Offset Error and Gain Error  
DAC CODE  
Figure 2. Gain Error  
–9–  
REV. 0  

与AD5336相关器件

型号 品牌 描述 获取价格 数据表
AD5336_15 ADI 2.5 V to 5.5 V, 500A, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs

获取价格

AD5336BRU ADI 2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs

获取价格

AD5336BRU-REEL7 ROCHESTER QUAD, PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO24, TSSOP-28

获取价格

AD5336BRUZ ADI 2.5 V to 5.5 V, 500 A, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs

获取价格

AD5336BRUZ-REEL7 ROCHESTER QUAD, PARALLEL, 8 BITS INPUT LOADING, 7us SETTLING TIME, 10-BIT DAC, PDSO24, TSSOP-28

获取价格

AD5337 ADI 2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs

获取价格