5秒后页面跳转
捷配首页

Datasheet > AD5307ARUZ-REEL71
AD5307ARUZ-REEL71 PDF预览

AD5307ARUZ-REEL71

更新时间： 2022-04-21 15:39:16
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 585K
描述
2.5 V to 5.5 V, 400 muA, Quad Voltage Output

阅读下载

中文翻译

获取价格

AD5307ARUZ-REEL71 数据手册

 浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第5页浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第6页浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第7页浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第9页浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第10页浏览型号AD5307ARUZ-REEL71的Datasheet PDF文件第11页 
AD5307/AD5317/AD5327  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
SDO  
CLR  
SYNC  
15  
LDAC  
AD5307/  
AD5317/ 14 SCLK  
AD5327  
V
DD  
13  
12  
11  
10  
9
DIN  
V
V
V
A
B
C
OUT  
OUT  
OUT  
TOP VIEW  
(Not to Scale)  
GND  
V
D
OUT  
V
AB  
CD  
PD  
REF  
DCEN  
V
REF  
Figure 5. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin  
No.  
Mnemonic Description  
1
CLR  
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.  
2
LDAC  
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this  
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous  
update of all DAC outputs. Alternatively, this pin can be tied permanently low.  
3
VDD  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF  
capacitor in parallel with a 0.1 μF capacitor to GND.  
4
5
6
7
VOUT  
VOUT  
VOUT  
A
B
C
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of  
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range  
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.  
VREFAB  
8
VREFCD  
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of  
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range  
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.  
9
DCEN  
PD  
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is  
being used in standalone mode.  
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this  
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to  
300 nA @ 5 V (90 nA @ 3 V).  
10  
11  
12  
13  
VOUT  
GND  
DIN  
D
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of  
the serial clock input. The DIN input buffer is powered down after each write cycle.  
14  
15  
SCLK  
SYNC  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be  
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.  
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers  
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the  
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and  
the write sequence is ignored by the device.  
16  
SDO  
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in  
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the  
falling edge of the clock.  
Rev. C | Page 8 of 28  
 
1...567891011...28

中文翻译

下载PDF

与AD5307ARUZ-REEL71相关器件

型号 品牌 获取价格 描述 数据表
AD5307BRU ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5307BRU-REEL ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5307BRU-REEL7 ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5307BRUZ ADI

获取价格

 		2.5 V to 5.5 V, 400 µA, Quad Voltage Output 8-Bit DAC in a 16-Lead TSSOP
AD5307BRUZ1 ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5307BRUZ-REEL ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5307BRUZ-REEL7 ADI

获取价格

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output
AD5308 ADI

获取价格

 		2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308_1 ADI

获取价格

 		2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308_11 ADI

获取价格

 		2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

与AD5307ARUZ-REEL71相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证