Datasheet > AD5307ARUZ-REEL71

AD5307ARUZ-REEL71

更新时间： 2022-04-21 15:39:16

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	585K
描述
2.5 V to 5.5 V, 400 muA, Quad Voltage Output

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AD5307ARUZ-REEL71 数据手册

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AD5307/AD5317/AD5327

AC CHARACTERISTICS

V_DD= 2.5 V to 5.5 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND. All specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A, B Versions¹

Parameter^{2, 3}

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5307

AD5317

V_REF= V_DD= 5 V

μs

1/4 scale to 3/4 scale change (0x40 to 0xC0)

1/4 scale to 3/4 scale change (0x100 to 0x300)

1/4 scale to 3/4 scale change (0x400 to 0xC00)

AD5327

Slew Rate

0.7

0.5

200

−70

V/μs

nV-s

kHz

Major-Code Change Glitch Energy

Digital Feedthrough

SDO Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB change around major carry

Daisy-chain mode; SDO load is 10 pF

V_REF= 2 V 0.1 V p-p; unbuffered mode

V_REF= 2.5 V 0.1 V p-p; frequency = 10 kHz

¹Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.

²Guaranteed by design and characterization; not production tested.

³See the Terminology section.

TIMING CHARACTERISTICS

V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

A, B Versions

ꢀimit at T_MIN, T_MAX

Parameter^{1, 2,}

Unit

Conditions/Comments

t₁

t₂

t₃

t₄

ns min

ns max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge set-up time

Data set-up time

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

t₅

t₆

t₇

4.5

t₈

t₉

LDAC pulse width

t₁₀

t₁₁

t₁₂

SCLK falling edge to LDAC rising edge

CLR pulse width

SCLK falling edge to LDAC falling edge

SCLK rising edge to SDO valid (V_DD= 3.6 V to 5.5 V)

SCLK rising edge to SDO valid (V_DD= 2.5 V to 3.5 V)

SCLK falling edge to SYNC rising edge

SYNC rising edge to SCLK rising edge

SYNC rising edge to LDAC falling edge

4, 5

t₁₃

t₁₄

t₁₅

t₁₆

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 3 and Figure 4.

⁴This is measured with the load circuit of Figure 2. t₁₃determines maximum SCLK frequency in daisy-chain mode.

⁵Daisy-chain mode only.

Rev. C | Page 5 of 28

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