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AD5293BRUZ-20 PDF预览

AD5293BRUZ-20

更新时间: 2024-02-28 03:19:09
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计
页数 文件大小 规格书
20页 687K
描述
Single-Channel, 1024-Position, 1% R-Tolerance Digital Potentiometer

AD5293BRUZ-20 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.72
其他特性:DEVICE SUPPORTS DUAL SUPPLY OPERATION标称带宽:0.52 kHz
控制接口:3-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:5 mm湿度敏感等级:1
标称负供电电压:-15 V功能数量:1
位置数:1024端子数量:14
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:+-10.5/+-16.5/21/33 V认证状态:Not Qualified
电阻定律:LINEAR最大电阻容差:1%
最大电阻器端电压:16.5 V最小电阻器端电压:-9 V
座面最大高度:1.2 mm子类别:Digital Potentiometers
标称供电电压:15 V表面贴装:YES
技术:CMOS标称温度系数:35 ppm/ °C
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:20000 Ω宽度:4.4 mm
Base Number Matches:1

AD5293BRUZ-20 数据手册

 浏览型号AD5293BRUZ-20的Datasheet PDF文件第14页浏览型号AD5293BRUZ-20的Datasheet PDF文件第15页浏览型号AD5293BRUZ-20的Datasheet PDF文件第16页浏览型号AD5293BRUZ-20的Datasheet PDF文件第18页浏览型号AD5293BRUZ-20的Datasheet PDF文件第19页浏览型号AD5293BRUZ-20的Datasheet PDF文件第20页 
AD5293  
If ignoring the effect of the wiper resistance for simplicity,  
connecting the A terminal to 30 V and the B terminal to ground  
produces an output voltage at the Wiper W to Terminal B that  
ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to  
the voltage applied across the A terminal and B terminal, divided  
by the 1024 positions of the potentiometer divider. The general  
equation defining the output voltage at VW, with respect to  
ground for any valid input voltage applied to Terminal A and  
Terminal B, is  
TERMINAL VOLTAGE OPERATING RANGE  
The positive VDD and negative VSS power supplies of the AD5293  
define the boundary conditions for proper 3-terminal, digital  
potentiometer operation. Supply signals present on the A, B,  
and W terminals that exceed VDD or VSS are clamped by the  
internal forward-biased diodes (see Figure 37).  
V
DD  
D
1024  
1024 D  
1024  
VW (D) =  
×VA +  
×VB  
(3)  
A
To optimize the wiper position update rate when in voltage  
W
B
divider mode, it is recommended that the internal 1% resistor  
tolerance calibration feature be disabled by programming Bit C2  
of the control register (see Table 9 and Table 10).  
Operation of the digital potentiometer in the divider mode  
results in a more accurate operation over temperature. Unlike  
when the part is in the rheostat mode, the output voltage is  
dependent mainly on the ratio of the internal resistors, RWA and  
RWB, not on the absolute values. Therefore, the temperature drift  
reduces to 5 ppm/°C.  
V
SS  
Figure 37. Maximum Terminal Voltages Set by VDD and VSS  
The ground pin of the AD5293 is primarily used as a digital  
ground reference. To minimize the digital ground bounce, the  
AD5293 ground pin should be joined remotely to common  
ground. The digital input control signals to the AD5293 must be  
referenced to the device ground pin (GND) to satisfy the logic  
level defined in the Specifications section.  
EXT_CAP CAPACITOR  
A 1 μF capacitor to GND must be connected to the EXT_CAP  
pin (see Figure 36) on power-up and throughout the operation  
of the AD5293. This capacitor must have a voltage rating of ≥7 V.  
Power-Up Sequence  
Because there are diodes to limit the voltage compliance at the  
A, B, and W terminals (see Figure 37), it is important to power  
AD5293  
V
DD and VSS first, before applying any voltage to the A, B, and W  
EXT_CAP  
C1  
1µF  
terminals. Otherwise, the diode is forward-biased such that VDD  
and VSS are powered up unintentionally. The ideal power-up  
sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then  
VA, VB, and VW. The order of powering up VA, VB, VW, and the  
digital inputs is not important, as long as they are powered after  
GND  
Figure 36. Hardware Setup for the EXT_CAP Pin  
VDD, VSS, and VLOGIC  
.
Regardless of the power-up sequence and the ramp rates of the  
power supplies, the power-on preset activates after VLOGIC is  
powered, restoring midscale to the RDAC register.  
Rev. 0 | Page 17 of 20  
 
 
 

AD5293BRUZ-20 替代型号

型号 品牌 替代类型 描述 数据表
AD5293BRUZ-20-RL7 ADI

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