Datasheet > AD5061YRJZ-1500RL7

AD5061YRJZ-1500RL7

更新时间： 2024-01-15 03:20:10

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		输入元件光电二极管转换器
页数	文件大小	规格书
21页	1730K
描述
SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN

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AD5061YRJZ-1500RL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	LSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.73
最大模拟输出电压：	4.096 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	2.9 mm
最大线性误差 (EL)：	0.0061%	湿度敏感等级：	1
位数：	16	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.45 mm
标称安定时间 (tstl)：	4 µs	标称供电电压：	3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	1.6 mm
Base Number Matches：	1

AD5061YRJZ-1500RL7 数据手册

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AD5061

AD5061-to-68HC11/68L11 Interface

AD5061-to-80C51/80L51 Interface

Figure ±2 shows a serial interface between the AD5061 and the

68HC11/68ꢀ11 microcontroller. LCK of the 68HC11/68ꢀ11

drives the LCꢀK pin of the AD5061, while the MOLI output

Figure ±± shows a serial interface between the AD5061 and the

80C51/80ꢀ51 microcontroller. The setup for the interface is:

TxD of the 80C51/80ꢀ51 drives LCꢀK of the AD5061 while

LYNC

drives the serial data line of the DAC. The

signal is

RxD drives the serial data line of the part. The

signal is

derived from a port line (PC7). The set-up conditions for

correct operation of this interface require that the 68HC11/

68ꢀ11 be configured so that its CPOꢀ bit is 0 and its CPHA bit

again derived from a bit-programmable pin on the port. In this

case, Port ꢀine P3.3 is used. When data is to be transmitted to

the AD5061, P3.3 is taken low. The 80C51/80ꢀ51 transmits data

only in 8-bit bytes; thus only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is left low after

the first eight bits are transmitted, and a second write cycle is

initiated to transmit the second byte of data. P3.3 is taken high

following the completion of this cycle. The 80C51/80ꢀ51 out-

puts the serial data in a format that has the ꢀLB first. The

AD5061 requires its data with the MLB as the first bit received.

The 80C51/80ꢀ51 transmit routine should take this into account.

LYNC

is 1. When data is being transmitted to the DAC, the

is taken low (PC7). When the 68HC11/68ꢀ11 is configured

line

where its CPOꢀ bit is 0 and its CPHA bit is 1, data appearing on

the MOLI output is valid on the falling edge of LCK. Lerial data

from the 68HC11/68ꢀ11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MLB first. To load data to the AD5061, PC7 is left

low after the first eight bits are transferred, a second serial write

operation is performed to the DAC, and PC7 is taken high at

the end of this procedure.

80C51/80L51¹

AD5061¹

68HC11/

AD5061¹

68L11¹

P3.3

SYNC

TxD

RxD

SCLK

DIN

PC7

SCK

SYNC

SCLK

DIN

ADDITIONAL PINS OMITTED FOR CLARITY

MOSI

Figure 44. AD5061-to-80C51/80L51 Interface

ADDITIONAL PINS OMITTED FOR CLARITY

AD5061-to-MICROWIRE Interface

Figure 42. AD5061-to-68HC11/68L11 Interface

Figure ±5 shows an interface between the AD5061 and any

MICROWIRE-compatible device. Lerial data is shifted out on

the falling edge of the serial clock and is clocked into the

AD5061 on the rising edge of the LK.

AD5061-to-Blackfin® ADSP-BF53x Interface

Figure ±3 shows a serial interface between the AD5061 and the

Blackfin ADLP-53x microprocessor. The ADLP-BF53x proces-

sor family incorporates two dual-channel synchronous serial

ports, LPORT1 and LPORT0, for serial and multiprocessor

communications. Using LPORT0 to connect to the AD5061,

the setup for the interface is: DT0PRI drives the DIN pin of

the AD5061, while TLCꢀK0 drives the LCꢀK of the part; the

AD5061¹

MICROWIRE¹

SYNC

SCLK

DIN

LYNC

is driven from TFL0.

AD5061¹

ADSP-BF53x¹

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. AD5061-to-MICROWIRE Interface

DT0PRI

DIN

TSCLK0

TFS0

SCLK

SYNC

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 43. AD5061-to-Blackfin ADSP-BF53x Interface

Rev. A | Page 17 of 20

1...15 16 171819 20 21

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与AD5061YRJZ-1500RL7相关器件

型号	品牌	获取价格	描述	数据表
AD5061YRJZ-1REEL7	ADI	获取价格	16-Bit VOUT, nanoDAC®, SPI Interface,
AD5062	ADI	获取价格	Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23
AD50621	ADI	获取价格	Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a T
AD5062ARJZ-1500RL7	ROCHESTER	获取价格	SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, ROHS COMPLIANT, MO-178BA, SOT
AD5062BRJ-1	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-1500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-2	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-2500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-3	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJZ-1REEL7	ADI	获取价格	2.7 V-5.5 V, Full Accurate 16-Bit VOUT nanoDAC® Converter, Unbuffered, in a Sot 23

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