Datasheet > AD5061YRJZ-1500RL7

AD5061YRJZ-1500RL7

更新时间： 2024-02-05 01:27:55

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		输入元件光电二极管转换器
页数	文件大小	规格书
21页	1730K
描述
SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD5061YRJZ-1500RL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	LSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.73
最大模拟输出电压：	4.096 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	2.9 mm
最大线性误差 (EL)：	0.0061%	湿度敏感等级：	1
位数：	16	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.45 mm
标称安定时间 (tstl)：	4 µs	标称供电电压：	3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	1.6 mm
Base Number Matches：	1

AD5061YRJZ-1500RL7 数据手册

浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第13页

浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第14页

浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第15页

浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第17页

浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第18页

AD5061

THEORY OF OPERATION

The AD5061 is a single 16-bit, serial input, voltage output DAC.

It operates from supply voltages of 2.7 V to 5.5 V. Data is writ-

ten to the AD5061 in a 2±-bit word format, via a 3-wire serial

interface.

LYNC

line low. Data

The write sequence begins by bringing the

from the DIN line is clocked into the 2±-bit shift register on the

falling edge of LCꢀK. The serial clock frequency can be as high

as 30 MHz, making these parts compatible with high speed

DLPs. On the 2±th falling clock edge, the last data bit is clocked

in and the programmed function is executed (that is, a change

in the DAC register contents and/or a change in the mode of

operation).

The AD5061 incorporates a power-on reset circuit that ensures

the DAC output powers up to zero-scale or midscale. The

device also has a software power-down mode pin that reduces

the typical current consumption to less than 1 µA.

LYNC

At this stage, the

line may be kept low or be brought

DAC ARCHITECTURE

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence so that a falling edge of

The DAC architecture of the AD5061 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 37. The four MLBs of the 16-bit data word are decoded

to drive 15 switches, E1 to E15. Each of these switches connects

one of 15 matched resistors to either DACGND or V_REFbuffer

output. The remaining 12 bits of the data word drive switches

L0 to L11 of a 12-bit voltage mode R-2R ladder network.

LYNC

can initiate the next write sequence. Because the

buffer draws more current when V_IH= 1.8 V than it does when

V_IH= 0.8 V, should be idled low between write sequences

LYNC

for an even lower power operation of the part. As previously

indicated, however, it must be brought high again just before

the next write sequence.

OUT

INPUT SHIFT REGISTER

The input shift register is 2± bits wide; see Figure 38. PD1 and

PD0 are control bits that control which mode of operation the

part is in (normal mode or any one of three power-down

modes). There is a more complete description of the various

modes in the Power-Down Modes section. The next 16 bits are

the data bits. These are transferred to the DAC register on the

2±th falling edge of LCꢀK.

E15

S11

REF

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 37. DAC Ladder Structure

REFERENCE BUFFER

SYNC INTERRUPT

The AD5061 operates with an external reference. The reference

input (V_REF) has an input range of 2 V to V_DD− 50 mV. This

input voltage is then used to provide a buffered reference for the

DAC core.

In a normal write sequence, the

line is kept low for at

LYNC

least 2± falling edges of LCꢀK and the DAC is updated on the

2±th falling edge. However, if is brought high before the

LYNC

2±th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs; see Figure ±1.

SERIAL INTERFACE

LYNC

The AD5061 has a 3-wire serial interface (

, LCꢀK, and

DIN), which is compatible with LPI, QLPI, and MICROWIRE

interface standards, as well as most DLPs. Lee Figure 2 for a

timing diagram of a typical write sequence.

DB15 (MSB)

DB0 (LSB)

PD1

PD0

D15

D14

D13

D12

D11

D10

DATA BITS

NORMAL OPERATION

3-STATE

100kΩ TO GND

1kΩ TO GND

POWER-DOWN MODES

Figure 38. Input Register Contents

Rev. A | Page 15 of 20

1...13 14 151617 18 19...21

中文翻译

下载PDF

与AD5061YRJZ-1500RL7相关器件

型号	品牌	获取价格	描述	数据表
AD5061YRJZ-1REEL7	ADI	获取价格	16-Bit VOUT, nanoDAC®, SPI Interface,
AD5062	ADI	获取价格	Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23
AD50621	ADI	获取价格	Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a T
AD5062ARJZ-1500RL7	ROCHESTER	获取价格	SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, ROHS COMPLIANT, MO-178BA, SOT
AD5062BRJ-1	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-1500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-2	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-2500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-3	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJZ-1REEL7	ADI	获取价格	2.7 V-5.5 V, Full Accurate 16-Bit VOUT nanoDAC® Converter, Unbuffered, in a Sot 23

与AD5061YRJZ-1500RL7相关文章

晶闸管阳极与阴极之间加电压时控制极的电流流动分析
2024-06-05

12
探究MOS管沟道夹断后载流子传输机制及其电路设计影响
2024-06-05

9
光敏电阻的工作原理、作用及检测方法
2024-06-05

8
ENC28J60以太网控制器全面解析：特性、应用、引脚说明
2024-06-05

6

产品中心

服务支持

精选活动

关于我们

帮助中心

AD5061YRJZ-1500RL7

AD5061YRJZ-1500RL7 技术参数

AD5061YRJZ-1500RL7 数据手册

与AD5061YRJZ-1500RL7相关器件

与AD5061YRJZ-1500RL7相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD5061YRJZ-1500RL7

AD5061YRJZ-1500RL7 技术参数

AD5061YRJZ-1500RL7 数据手册

与AD5061YRJZ-1500RL7相关器件

与AD5061YRJZ-1500RL7相关文章

您还可以找

您在本页遇到什么问题？