Datasheet > AD5061YRJZ-1500RL7

AD5061YRJZ-1500RL7

更新时间： 2024-01-18 15:41:32

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		输入元件光电二极管转换器
页数	文件大小	规格书
21页	1730K
描述
SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN

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AD5061YRJZ-1500RL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	LSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.73
最大模拟输出电压：	4.096 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	2.9 mm
最大线性误差 (EL)：	0.0061%	湿度敏感等级：	1
位数：	16	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.45 mm
标称安定时间 (tstl)：	4 µs	标称供电电压：	3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	1.6 mm
Base Number Matches：	1

AD5061YRJZ-1500RL7 数据手册

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AD5061

OUTPUT

BUFFER

POWER-ON TO ZERO-SCALE OR MIDSCALE

AD5061

OUT

DAC

The AD5061 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

the zero-scale or midscale code and the output voltage is zero-

scale or midscale. It remains there until a valid write sequence is

made to the DAC. This is useful in applications where it is

important to know the state of the output of the DAC while it is

in the process of powering up.

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 39. Output Stage During Power-Down

SOFTWARE RESET

The bias generator, the DAC core and other associated linear

circuitry are all shut down when the power-down mode is

activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit power-down

is typically 2.5 µs for V_DD= 5 V, and 5 µs for V_DD= 3 V;

see Figure 19.

The device can be put into software reset by setting all bits in

the DAC register to 1; this includes writing 1s to Bit D23 to

Bit D16, which is not the normal mode of operation. Note that

the

interrupt command cannot be performed if a

LYNC

software reset command is started.

MICROPROCESSOR INTERFACING

POWER-DOWN MODES

AD5061-to-ADSP-2101/ADSP-2103 Interface

The AD5061 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 6 shows how the state

of the bits corresponds to the mode of operation of the device.

Figure ±0 shows a serial interface between the AD5061 and the

ADLP-2101/ADLP-2103. The ADLP-2101/ADLP-2103 should

be set up to operate in the LPORT transmit alternate framing

mode. The ADLP-2101/ADLP-2103 LPORT is programmed

through the LPORT control register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. Transmission is initiated by writing a word to the

Tx register after the LPORT has been enabled.

Table 6. Modes of Operation

DB17

DB16

Operating Mode

Normal operation

Power-down mode:

3-state

100 kΩ to GND

1 kΩ to GND

ADSP-2101/

AD5061

ADSP-2103¹

When both bits are set to 0, the part works normally with its

normal power consumption. However, for the three power-

down modes, the supply current falls to less than 1μA at 5 V

(265 nA at 3 V). Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through a

1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited

(3-state). The output stage is illustrated in Figure 39.

TFS

SYNC

DIN

SCLK

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 40. AD5061-to-ADSP-2101/ADSP-2103 Interface

SCLK

SYNC

DIN

DB23

DB0

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24 FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24 FALLING EDGE

SYNC

Figure 41.

Interrupt Facility

Rev. A | Page 16 of 20

1...14 15 161718 19 20 21

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与AD5061YRJZ-1500RL7相关器件

型号	品牌	获取价格	描述	数据表
AD5061YRJZ-1REEL7	ADI	获取价格	16-Bit VOUT, nanoDAC®, SPI Interface,
AD5062	ADI	获取价格	Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23
AD50621	ADI	获取价格	Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a T
AD5062ARJZ-1500RL7	ROCHESTER	获取价格	SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, ROHS COMPLIANT, MO-178BA, SOT
AD5062BRJ-1	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-1500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-2	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJ-2500RL7	ADI	获取价格	IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to
AD5062BRJ-3	ADI	获取价格	Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
AD5062BRJZ-1REEL7	ADI	获取价格	2.7 V-5.5 V, Full Accurate 16-Bit VOUT nanoDAC® Converter, Unbuffered, in a Sot 23

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