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AD5045BRUZ

更新时间： 2024-10-28 03:17:47
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管PC
页数 文件大小 规格书
33页 755K
描述
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP

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中文翻译

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AD5045BRUZ 数据手册

 浏览型号AD5045BRUZ的Datasheet PDF文件第6页浏览型号AD5045BRUZ的Datasheet PDF文件第7页浏览型号AD5045BRUZ的Datasheet PDF文件第8页浏览型号AD5045BRUZ的Datasheet PDF文件第10页浏览型号AD5045BRUZ的Datasheet PDF文件第11页浏览型号AD5045BRUZ的Datasheet PDF文件第12页 
Preliminary Technical Data  
AD5025/45/65  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
14  
13  
12  
1
2
3
4
5
6
7
LDAC  
SCLK  
DIN  
SYNC  
V
PDL  
DD  
AD5065/45/35  
11  
10  
VrefA  
GND  
TOP VIEW  
(Not to Scale)  
V
B
V
A
OUT  
OUT  
9
8
VrefB  
CLR  
POR  
SDO  
Figure 5. 14-Lead TSSOP (RU-14)  
Table 6. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
LDAC  
Pulsing this pin low allows any or all DAC registers to be updated if the input registers  
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this  
pin can be tied permanently low.  
2
SYNC  
Active Low Control Input. This is the frame synchronization signal for the input data.  
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input  
shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is  
taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt  
and the write sequence is ignored by the device.  
3
VDD  
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply  
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to  
GND.  
4
5
6
VREFA  
Dac A reference input .This is the reference voltage input pin for Dac A.  
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to  
VDD powers up the part to midscale.  
VOUT  
A
POR  
7
SDO  
Serial Data Output. Can be used for daisy-chaining a number of these devices  
together or for reading back the data in the shift register for diagnostic purposes. The  
serial data is transferred on the rising edge of SCLK and is valid on the falling edge of  
the clock.  
8
CLR  
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low,  
all LDAC pulses are ignored. When CLR is activated, the input register and the DAC  
register are updated with the data contained in the CLR code register—zero,  
midscale, or full scale. Default setting clears the output to 0 V.  
9
VREFB  
Dac B reference input .This is the reference voltage input pin for Dac B.  
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
The PDL pin is used to ensure hardware shutdown lockout of the device under any  
circumstance. A Logic 1 at the PLO pin will cause the device to behave as normal.  
The user may successfully enter software power down over the serial interface while  
logic 1 is applied to the PDL pin.  
10  
11  
12  
VOUT  
GND  
PDL  
B
If a logic 0 is applied to this pin, it will ensure that the device cannot enter software  
power down under any circumstances. If the device had previously been placed in  
software power down mode, a high to low transition at the PDL pin will cause the  
DAC(s) to exit power down and the output the last code in the dac register before  
the device entered software power down.  
13  
14  
DIN  
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the  
register on the falling edge of the serial clock input.  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the  
serial clock input. Data can be transferred at rates of up to 50 MHz.  
SCLK  
Rev. PrB | Page 9 of 33  
1...6789101112...33

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AD5045BRUZ 替代型号

型号 品牌 替代类型 描述 数据表
AD5045BRUZ-REEL7 ADI

完全替代

 Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
AD5025BRUZ-REEL7 ADI

类似代替

 Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
AD5025BRUZ ADI

类似代替

 Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP

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