AD1674
R1
100k
REFERENCE D ECO UP LING
2
12/8
CS
STS 28
It is recommended that a 10 µF tantalum capacitor be con-
nected between REF IN (Pin 10) and ground. T his has the
effect of improving the S/(N+D) ratio through filtering possible
broad-band noise contributions from the voltage reference.
3
4
HIGH BITS
24-27
+15V
–15V
A
0
5
6
R/C
CE
MIDDLE BITS
20-23
R2
100Ω
100k
100Ω
10 REF IN
LOW BITS
16-19
8
REF OUT
BO ARD LAYO UT
12 BIP OFF
Designing with high resolution data converters requires careful
attention to board layout. T race impedance is a significant issue.
At the 12-bit level, a 5 mA current through a 0.5 Ω trace will
develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V
full-scale range. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies should be decoupled in order to
filter out ac noise.
AD1674
+5V
+15V
1
7
0 TO +10V
ANALOG
INPUTS
13 10V
14 20V
IN
–15V 11
IN
0 TO +20V
9
ANA COM DIG COM 15
Figure 11. Unipolar Input Connections with Gain and
Offset Trim s
T he full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 V for a 10 V range) and adjusting
R2 until the last transition is located (1111 1111 1110 to 1111
1111 1111). If full-scale adjustment is not required, R2 should
be replaced with a fixed 50 Ω ±1% metal film resistor. If REF
OUT is connected directly to REF IN, the additional full-scale
error will be approximately 1%.
T he AD1674 has a wide bandwidth sampling front end. T his
means that the AD1674 will “see” high frequency noise at the
input, which nonsampling (or limited-bandwidth sampling)
ADCs would ignore. T herefore, it’s important to make an effort
to eliminate such high frequency noise through decoupling or by
using an anti-aliasing filter at the analog input of the AD1674.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them (if necessary) only at right angles.
BIP O LAR RANGE INP UTS
T he connections for the bipolar-input mode are shown in Figure
12. Either or both of the trimming potentiometers can be
replaced with 50 Ω ± 1% fixed resistors if the specified AD1674
accuracy limits are sufficient for the application. If the pins are
shorted together, the additional offset and gain errors will be
approximately 1%.
T o trim bipolar offset to its nominal value, apply a signal 1/2
LSB below midrange (–1.22 mV for a ±5 V range) and adjust
R1 until the major carry transition is located (0111 1111 1111
to 1000 0000 0000). T o trim the full-scale error, apply a signal
1 1/2 LSB below full scale (+4.9963 V for a ±5 V range) and
adjust R2 to give the last positive transition (1111 1111 1110 to
1111 1111 1111). T hese trims are interactive so several itera-
tions may be necessary for convergence.
T he AD1674 incorporates several features to help the user’s lay-
out. Analog pins are adjacent to help isolate analog from digital
signals. Ground currents have been minimized by careful circuit
architecture. Current through AGND is 2.2 mA, with little
code-dependent variation. T he current through DGND is domi-
nated by the return current for DB11–DB0.
A single-pass calibration can be done by substituting a negative
full-scale trim for the bipolar offset trim (error at midscale),
using the same circuit. First, apply a signal 1/2 LSB above minus
full scale (–4.9988 V for a ±5 V range) and adjust R1 until the
minus full-scale transition is located (0000 0000 0001 to 0000
0000 0000). Then perform the gain error trim as outlined above.
SUP P LY D ECO UP LING
T he AD1674 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 µF tanta-
lum capacitor in parallel with a 0.1 µF disc ceramic capacitor
provides adequate decoupling over a wide range of frequencies.
2
12/8
CS
STS 28
3
4
HIGH BITS
24-27
A
0
5
6
R/C
CE
MIDDLE BITS
20-23
R2
100Ω
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. T he circuit layout should attempt to locate
the AD1674, associated analog input circuitry, and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD1674 will isolate large switching
ground currents. For these reasons, the use of wire-wrap circuit
construction is not recommended; careful printed-circuit con-
struction is preferred.
10 REF IN
LOW BITS
16-19
8
REF OUT
12 BIP OFF
R1
100Ω
AD1674
+5V
+15V
1
7
±5V
13 10V
14 20V
IN
ANALOG
INPUTS
±10V
–15V 11
IN
9
ANA COM DIG COM 15
Figure 12. Bipolar Input Connections with Gain and Offset
Trim s
REV. C
–11–
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