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ACTS373DMSR

更新时间： 2024-11-10 22:49:55
品牌 Logo 应用领域
英特矽尔 - INTERSIL 锁存器逻辑集成电路驱动
页数 文件大小 规格书
10页 93K
描述
Radiation Hardened Octal Transparent Latch, Three-State

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ACTS373DMSR 数据手册

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ACTS373MS  
Radiation Hardened  
Octal Transparent Latch, Three-State  
April 1995  
Features  
• 1.25 Micron Radiation Hardened SOS CMOS  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C  
TOP VIEW  
• Total Dose 300K RAD (Si)  
• Single Event Upset (SEU) Immunity  
<1 x 10-10 Errors/Bit-Day (Typ)  
• SEU LET Threshold >80 MEV-cm2/mg  
1
2
3
4
5
6
7
8
9
VCC  
Q7  
OE  
Q0  
D0  
D1  
Q1  
Q2  
D2  
D3  
Q3  
20  
19  
18 D7  
17 D6  
16 Q6  
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
15  
Q5  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range: 4.5V to 5.5V  
14 D5  
13 D4  
12  
Q4  
• Input Logic Levels  
- VIL = 0.8V Max  
GND 10  
11 LE  
20 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C  
TOP VIEW  
- VIH = VCC/2V Min  
• Input Current ≤1µA at VOL, VOH  
OE  
Q0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
Q7  
D7  
D6  
Q6  
Q5  
D5  
D4  
Q4  
LE  
Description  
The Intersil ACTS373MS is a radiation hardened octal transpar-  
ent latch with three-state outputs. The outputs are transparent to  
the inputs when the latch enable (LE) is high. When the LE goes  
low, the data is latched. When the Output Enable (OE) is high,  
the outputs are in the high impedance state. The latch operation  
is independent of the state of the output enable.  
D0  
D1  
Q1  
Q2  
D2  
D3  
The ACTS373MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of the  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Q3  
GND  
Ordering Information  
PART NUMBER  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
ACTS373DMSR  
-55 C to +125 C  
20 Lead SBDIP  
o
o
ACTS373KMSR  
-55 C to +125 C  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
ACTS373D/Sample  
ACTS373K/Sample  
ACTS373HMSR  
+25 C  
o
+25 C  
Sample  
20 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
Truth Table  
Functional Diagram  
1 OF 8  
OE  
LE  
H
H
L
D
H
L
I
Q
H
L
(3, 4, 7, 8, 13,  
14, 17, 18)  
LATCH  
L
OE  
D
D
Q
Q
L
(2, 5, 6, 9, 12,  
15, 16, 19)  
COMMON  
CONTROLS  
LE  
L
L
L
H
L
h
X
H
Z
LE  
(11)  
X
NOTE:  
L
= Low Voltage Level  
X = Don’t Care  
Z = High Impedance State  
OE  
(1)  
H = High Voltage Level  
I
h
= Low voltage level one set-up time prior to the high to low latch enable transition  
= High voltage level one set-up time prior to the high to low latch enable transition  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518800  
File Number 4000  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
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