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ACS8515LC PDF预览

ACS8515LC

更新时间： 2024-02-27 12:04:01
品牌 Logo 应用领域
商升特 - SEMTECH 开关
页数 文件大小 规格书
47页 590K
描述
Line Card Protection Switch for SONET or SDH Network Elements

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ACS8515LC 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：64
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
JESD-30 代码：S-PQFP-G64JESD-609代码：e0
长度：10 mm湿度敏感等级：3
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

ACS8515LC 数据手册

 浏览型号ACS8515LC的Datasheet PDF文件第5页浏览型号ACS8515LC的Datasheet PDF文件第6页浏览型号ACS8515LC的Datasheet PDF文件第7页浏览型号ACS8515LC的Datasheet PDF文件第9页浏览型号ACS8515LC的Datasheet PDF文件第10页浏览型号ACS8515LC的Datasheet PDF文件第11页 
ACS8515 LC/P  
FINAL  
ADVANCED COMMUNCIATIONS  
Default  
Priority  
(Note 3)  
Input Port  
Technology  
Port Name  
SEC1  
Frequencies Supported  
SEC Source Group  
Up to 100MHz (Note 1)  
Default (SONET):  
Default (SDH):  
TTL/CMOS  
8kHz  
8kHz  
1
2
1
2
1 (4)  
3 (5)  
2 (6)  
4 (7)  
Up to 100MHz (Note 1)  
Default (SONET):  
Default (SDH):  
SEC2  
TTL/CMOS  
8kHz  
8kHz  
Up to 155.52MHz (Note 2)  
Default (SONET):  
Default (SDH):  
LVDS/PECL  
LVDS default  
SEC1  
19.44MHz  
19.44MHz  
Up to 155.52MHz (Note 2)  
Default (SONET):  
Default (SDH):  
PECL/LVDS  
PECL default  
SEC2  
19.44MHz  
19.44MHz  
Up to 100MHz (Note 1)  
Default (SONET):  
Default (SDH):  
SEC3  
TTL/CMOS  
TTL/CMOS  
19.44MHz  
19.44MHz  
3
-
5 (10)  
-
SYNC1  
2kHz Multi Frame Sync  
Table 1: Input Reference Source Selection and Group allocation  
Notes for Table 1.  
Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency  
being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz,  
38.88 MHz, 51.84 MHz and 77.76 MHz.  
Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output  
clock frequencies available for SONET and SDH applications. F1/F2 means that the output frequency is F1 for SONET mode  
selection and F2 for SDH mode selection.  
Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the  
ACS8510.  
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by  
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.  
locking. The cnfg_freq_divn register contains input set to DivN must have the frequency  
the divider ratio N where the reference input monitors disabled (if the frequency monitors  
will get divided by (N+1) where 0<N<214-1. The are disabled, they are disabled for all inputs  
cnfg_ref_source_frequency register must be set regardless of the input configurations, in this  
to the closest supported spot frequency to the case only activity monitoring will take place).  
input frequency, but must be lower than the Whilst any number of inputs can be set to use  
input frequency. When using the “DivN” feature the “DivN” feature, only one N can be  
the post-divider frequency must be 8 kHz, which programmed, hence all inputs using the “DivN”  
is indicated by setting the ‘lock8k’ bit high (bit feature must require the same division to get  
6 in cnfg_ref_source_frequency register). Any to 8 kHz.  
Revision 2.05/Jan 2001 ã2001 Semtech Corp  
8
www.semtech.com  
1...567891011...47

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