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ACS8526 PDF预览

ACS8526

更新时间: 2024-01-06 10:59:25
品牌 Logo 应用领域
商升特 - SEMTECH 开关光电二极管
页数 文件大小 规格书
74页 801K
描述
Line Card Protection Switch for PDH, SONET or SDH Systems

ACS8526 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.41应用程序:SONET;SDH
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3,3.3/5 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Digital Transmission Interfaces
最大压摆率:0.2 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

ACS8526 数据手册

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ACS8526 LC/P LITE  
Line Card Protection Switch for PDH, SONET  
or SDH Systems  
ADVANCED COMMUNICATIONS  
Description  
FINAL  
Features  
DATASHEET  
The ACS8526 is a highly integrated single-chip solution  
for protection switching between two SECs (SDH/SONET  
Equipment Clocks) from Master and Slave SETS clock  
cards, for line cards in a PDH, SONET or SDH Network  
Element. The ACS8526 has fast activity monitors on the  
inputs and will raise a flag on a pin if there is a loss of  
activity on the currently selected input. The protection  
switching between the input reference clock sources is  
controlled by an external pin.  
‹ Line card protection switch - partners Semtech SETS  
devices for Stratum 3E/3/4E/4 PDH, SONET or SDH  
applications  
‹ High performance DPLL/APLL solution  
‹ Output jitter compliant to STM-1  
‹ Two independent SEC inputs ports (TTL)  
‹ Four independent output ports:  
‹ Two clock ports: one PECL/LVDS, one TTL  
‹ Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync  
‹ TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz  
‹ PECL/LVDS port: spot frequencies 2 kHz to 311 MHz  
‹ N x E1/DS1 mode  
The ACS8526 has two SEC reference clock input ports,  
configured for expected frequency by setting hardware  
pins or by writing to registers via the serial interface.  
The ACS8526 can perform frequency translation,  
converting, for example, an 8 kHz SEC input clock from a  
backplane into a 155.52 MHz clock for local line cards.  
‹ Programmable pulse width and polarity on Syncs  
‹ SONET/SDH frequency translation  
‹ Digital Holdover mode on input failure  
The ACS8526 generates two independent SEC clock  
outputs, one on a PECL/LVDS port and one on a  
TTL/CMOS port, at spot frequencies configured by  
hardware pins, or by writing to registers via the serial  
interface. The hardware selectable spot frequencies  
range from 1.544 MHz up to 155.52 MHz, with further  
options for N x E1/DS1 and 311.04 MHz via register  
selection. The ACS8526 also provides an 8 kHz Frame  
Sync output and 2 kHz Multi-Frame Sync output, both with  
programmable pulse width and polarity.  
‹ Separate activity monitors and register alarms on  
each input.  
‹ “Loss of activity” on selected input flagged on  
dedicated pin  
‹ Source switch under external hardware control  
‹ PLL “Locked” and “Acquisition” bandwidth selectable  
from 18, 35 or 70 Hz  
‹ Configurable via serial interface or hardware pins  
‹ Output clock phase continuity to GR-1244-CORE[13]  
‹ Single 3.3 V operation, 5 V I/O compatible  
‹ IEEE 1149.1 JTAG Boundary Scan is supported  
‹ Operating temperature (ambient) of -40 to +85°C  
‹ Available in LQFP 64 package  
Advanced configuration possibilities are available via the  
serial port (which can be SPI compatible), however the  
basic configuration of I/O frequencies and SONET/SDH  
selection by hardware make the device suitable for  
standalone operation, i.e., no need for a microprocessor.  
‹ Lead (Pb)-free version available (ACS8526T), RoHS  
Block Diagram  
and WEEE compliant.  
Figure 1 Block Diagram of the ACS8526 LC/P LITE  
LOS_ALARM  
IP_FREQ  
SONSDHB  
SEC Outputs:  
DPLL1  
DPLL2  
01 (LVDS/PECL)  
MUX  
2
2 x SEC TTL inputs  
APLL2  
Output  
Port  
Frequency  
Selection  
02 (TTL)  
SEC1  
SEC Inputs:  
Programmable  
Frequencies  
N x 8 kHz  
1.544 MHz  
2.048 MHz  
6.48 MHz  
Input  
SEC Port  
Selector  
Digital Feedback  
APLL3  
Sync Outputs:  
E1/DS1  
Synthesis  
SEC2  
MFrSync 2 kHz (TTL)  
FrSync 8 kHz (TTL)  
MUX  
1
APLL 1  
19.44 MHz  
Output Frequencies/MHz  
SRCSW  
25.92 MHz  
38.88 MHz  
51.84 MHz  
77.76 MHz  
01 Output:  
19.44  
02 Output:  
1.544  
TCK  
TDI  
TMS  
TRST  
TDO  
Chip  
Clock  
Generator  
IEEE  
1149.1  
JTAG  
25.92  
2.048  
SPI Compatible  
Serial Interface  
Port  
Priority  
Table  
Register Set  
34.368 (E3)  
38.88  
3.088  
19.44  
44.736 (DS3) 25.92  
51.84  
34.368 (E3)  
77.76  
38.88  
155.52  
44.736 (DS3)  
51.84  
77.76  
TCXO or  
XO  
F8526D_001BLOCKDIA_03  
OP_FREQ1  
OP_FREQ2  
Revision 4.01/June 2006 © Semtech Corp.  
Page1  
www.semtech.com  

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