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ACS8515LC

更新时间： 2024-02-03 11:14:53

品牌	Logo	应用领域
商升特 - SEMTECH		开关
页数	文件大小	规格书
47页	590K
描述
Line Card Protection Switch for SONET or SDH Network Elements

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技术参数
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ACS8515LC 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	64
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

ACS8515LC 数据手册

ACS8515 LC/P

FINAL

ADVANCED COMMUNCIATIONS

important than the stability since any frequency and left floating (in which case one input is

offset can be compensated by adjustment of internally pulled high and the other low).

SDH and SONET networks use different default

calibration and compensation of any crystal

frequencies; the network type is selectable

frequency variation away from its nominal value.

using the config_mode register 34 Hex, bit 2.

For SONET, config_mode register 34 Hex, bit 2

= 1, for SDH config_mode register 34 Hex, bit

+/- 50 ppm adjustment would be sufficient to

cope with most crystals, in fact the range is an

order of magnitude larger due to the use of

2 = 0. On power-up or by reset, the default will

two 8 bit register locations. The setting of the

be set by the state of the SONSDHB pin (pin

conf_nominal_frequency register allows for this

64). Specific frequencies and priorities are set

adjustment. An increase in the register value

by configuration.

increases the output frequencies by 0.02 ppm

for each LSB step. The default value (in decimal)

The TTL ports (compatible also with CMOS

is 39321. The minimum being 0 and the

signals) support clock speeds up to 100 MHz,

maximum 65535, gives a +500 ppm to -700

with the highest spot frequency being 77.76

ppm adjustment range of the output

MHz. Clock speeds above 100 MHz should not

be applied to the TTL ports. The PECL/LVDS

frequencies.

ports support the full range of clock speeds,

up to 155.52 MHz.

For example, if the crystal was oscillating at

12.8 MHz + 5ppm, then the calibration value

in the register to give a -5 ppm adjustment in

output frequencies to compensate for the

kHz (and N x 8 kHz), 1.544 MHz/2.048 MHz,

crystal inaccuracy, would be : 39321 - (5 /

The actual spot frequencies supported are; 8

6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,

51.84 MHz, 77.76 MHz, and 155.52 MHz. The

0.02) = 39071 (decimal).

frequency selection is programmed via the

Input Interfaces

cnfg_ref_source_frequency register. The

internal DPLL will normally lock to the selected

input at the frequency of the input, eg. 19.44

MHz will lock the DPLL phase comparisons at

19.44 MHz. It is, however, possible to utilise

an internal pre-divider to the DPLL to divide the

input frequency before it is used for phase

comparisons in the DPLL. This pre-divider can

be used in one of 2 ways;

The ACS8515 supports up to three individual

input reference clock sources via TTL/CMOS

and PECL/LVDS technologies. These interface

technologies support 3.3 V and 5 V operation.

Input Reference Clock Ports

The input reference clock ports are arranged in

groups. Group one comprises a TTL port (SEC1)

and a PECL/LVDS port (SEC1POS and

SEC1NEG). Group two comprises a TTL port

(SEC2) and a PECL/LVDS port (SEC2POS and

SEC2NEG). Group three comprises a TTL port

(SEC3). For group one and group two, only one

of the two input ports types must be active at

any time, the other must not be driven by a

reference input. Unused PECL/LVDS differential

inputs should be fixed with one input high (VDD)

and the other low (GND), or set in LVDS mode

(i) any of the supported spot frequencies can be divided to

8 kHz by setting the "lock8K" bit (bit 6) in the appropriate

cnfg_ref_source_frequency register location

(ii) any multiple of any supported frequency can be

supported by using the "DivN" feature (bit 7 of the

cnfg_ref_source_frequency register). Any reference input

can be set to lock at 8 kHz independently of the

frequencies and configurations of the other inputs.

Any reference input with the "DivN" bit set in

the cnfg_ref_source_frequency register will

employ the internal pre-divider prior to the DPLL

Revision 2.05/Jan 2001 ã2001 Semtech Corp

www.semtech.com

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与ACS8515LC相关器件

型号	品牌	描述	获取价格	数据表
ACS8515P	SEMTECH	Line Card Protection Switch for SONET or SDH Network Elements	获取价格
ACS8515REV2.1	SEMTECH	Line Card Protection Switch for SONET or SDH Network Elements	获取价格
ACS8515REV2.1LC/P	ETC	Line Card Protection Switch for SONET or SDH Network Elements	获取价格
ACS8515REV2.1T	SEMTECH	Line Card Protection Switch for SONET or SDH Network Elements	获取价格
ACS8515T	SEMTECH	Support Circuit, 1-Func, PQFP64, ROHS COMPLIANT, PLASTIC, LQFP-64	获取价格
ACS8520	SEMTECH	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems	获取价格

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