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ACS8515LC PDF预览

ACS8515LC

更新时间： 2024-01-03 06:24:29
品牌 Logo 应用领域
商升特 - SEMTECH 开关
页数 文件大小 规格书
47页 590K
描述
Line Card Protection Switch for SONET or SDH Network Elements

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ACS8515LC 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：64
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
JESD-30 代码：S-PQFP-G64JESD-609代码：e0
长度：10 mm湿度敏感等级：3
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

ACS8515LC 数据手册

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ACS8515 LC/P  
FINAL  
ADVANCED COMMUNCIATIONS  
PIN  
52  
SYMBOL  
SDO  
IO  
O
TYPE  
TTLD  
TTL  
NAME/DESCRIPTION  
Microprocessor interface address: Serial data output  
Output reference: 19.44 MHz fixed  
56  
O2  
O
SONETSDHB: SONET or SDH frequency select: sets the initial  
power up state (or state after a PORB) of the SONET/SDH  
frequency selection registers, addr 34h, bit 2 and addr 38, bit 5.  
When low SDH rates are selected (2.048 MHz etc) and when set  
high SONET rates are selected (1.544 MHz etc). The register states  
can be changed after power up by software  
64  
SONSDHB  
I
TTLD  
programmable (0.1 Hz up to 20 Hz cut-off  
points).  
Functional description  
The ACS8515 is a highly integrated, single-chip  
solution for “hit-less” protection switching of  
SEC clocks from Master and Slave SETS clock  
cards in a SONET or SDH Network Element.  
The ACS8515 has fast activity monitors on the  
inputs and will implement automatic system  
protection switching for Master/Slave SEC clock  
failure. The standby SEC clock will be selected  
if both the Master and Slave input clocks fail.  
The selection of the Master/Slave input can  
also be forced by a Force Fast Switch pin.  
The ACS8515 includes an SPI compatible serial  
microprocessor port, providing access to the  
configuration and status registers for device  
setup.  
Local Oscillator Clock  
The Master system clock on the ACS8515  
should be provided by an external clock oscillator  
of frequency 12.80 MHz. The exact clock  
specification is dependent on the quality of  
The ACS8515 can perform frequency translation Holdover performance required in the  
from a SEC input clock distributed along a back application.  
plane to a different local line card - e.g. 8 kHz  
distributed on the back plane and 19.44 MHz  
In most Line Card protection switching  
generated on the line cards.  
applications where there is a high chance that  
at least one SEC reference input will be  
available, the long term stability requirement  
for Holdover is not appropriate and an  
inexpensive crystal local oscillator can be used.  
In other applications where there may be a  
requirement for longer term Holdover stability  
to meet the ITU standards for Stratum 3, a  
higher quality oscillator can be used.  
The ACS8515 has three SEC clock inputs  
(Master, Slave and Standby) and a single Multi-  
Frame Sync input, for synchronising the frame  
and multi-frame sync outputs.  
The ACS8515 generates two SEC clock outputs  
via PECL/LVDS and TTL ports, with spot  
frequencies from 1.544/2.048 MHz up to  
311.04 MHz. The ACS8515 also provides an 8  
kHz Frame Sync and 2 kHz Multi-Frame Sync  
output clock.  
Please contact Semtech for information on  
crystal oscillator suppliers.  
The ACS8515 has a high tolerance to input  
jitter and wander. The output jitter and wander  
are low, where the wander transfer is  
Crystal Frequency Calibration  
The absolute crystal frequency accuracy is less  
Revision 2.05/Jan 2001 ã2001 Semtech Corp  
6
www.semtech.com  
1...3456789...47

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