Datasheet > ACS8510REV2.1T

ACS8510REV2.1T

更新时间： 2024-01-01 17:47:10

品牌	Logo	应用领域
商升特 - SEMTECH		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
76页	788K
描述
Support Circuit,

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技术参数
数据手册

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ACS8510REV2.1T 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.77	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
Base Number Matches：	1

ACS8510REV2.1T 数据手册

ACS8510 Rev2.1 SETS

FINAL

ADVANCED COMMUNICATIONS

Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25)

t_su1

t_su2

t_d1

t_d2

Setup SDI valid to SCLK_{rising edge}

Setup CSB_{falling edge}to SCLK_{rising edge}

0 ns

160 ns

Delay SCLK_{rising edge}(SCLK_{falling edge}for CLKE = 1) to SDO valid

Delay CSB_{rising edge}to SDO high-Z

17 ns

10 ns

SCLK low time

CLKE = 0

CLKE = 1

t_pw1

250ns

500ns

SCLK high time

CLKE = 0

CLKE = 1

t_pw2

250ns

500ns

t_h1

t_h2

t_p

Hold SDI valid after SCLK_{rising edge}

170 ns

5 ns

Hold CSB low after SCLK_{rising edge}, for CLKE = 0

Hold CSB low after SCLK_{falling edge}, for CLKE = 1

Time between consecutive accesses (CSB_{rising edge}to CSB_{falling edge}

)

160 ns

Figure 26. Write Access Timing in SERIAL Mode

CSB

su2

pw2

ALE=SCLK

A(0)=SDI

pw1

su1

R/W

A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7

Output not driven, pulled low by internal resistor

AD(0)=SDO

F8110D_014WriteAccSerial_02

Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26)

Symbol

t_su1

Parameter

Setup SDI valid to SCLK_{rising edge}

MIN

0 ns

TYP

MAX

t_su2

Setup CSB_{falling edge}to SCLK_{rising edge}

160 ns

t_pw1

t_pw2

t_h1

t_h2

t_p

SCLK low time

180 ns

170 ns

5 ns

SCLK high time

Hold SDI valid after SCLK_{rising edge}

Hold CSB low after SCLK_{rising edge}

Time between consecutive accesses (CSB_{rising edge}to CSB_{falling edge}

)

160 ns

Revision 2.00/September 2003 Semtech Corp.

www.semtech.com

1...67 68 697071 72 73...76

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