Datasheet > ACS422D68TAGZBX8

ACS422D68TAGZBX8

更新时间： 2024-02-20 12:59:12

品牌	Logo	应用领域
艾迪悌 - IDT		PC 电信电信集成电路
页数	文件大小	规格书
93页	1733K
描述
PCM Codec

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技术参数
数据手册

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ACS422D68TAGZBX8 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.6	JESD-609代码：	e3
湿度敏感等级：	3	电信集成电路类型：	PCM CODEC
端子面层：	Matte Tin (Sn)	Base Number Matches：	1

ACS422D68TAGZBX8 数据手册

浏览型号ACS422D68TAGZBX8的Datasheet PDF文件第10页

浏览型号ACS422D68TAGZBX8的Datasheet PDF文件第11页

ACS422x68

LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC

1. OVERVIEW

1.1. Block Diagrams

The ACS422x68 is an advanced low power codec with integrated amplifiers and timing generators. To support the

design of audio subsystems in a portable device, the ACS422x68 features an intelligent codec architecture with

advanced audio processing algorithms, integrated with a true cap-less headphone amplifier, 1W/channel (8) or

2W/channel (4) filterless DDX stereo class D amplifier, and microphone interface with programmable gain.

_PVDD4

_V-2

_CAP-2

_AVDD3

CPVDD

CAP+

Clocking

DVDD_CORE

DVDD_IO

VDD_XTAL

VDD_PLL2

Class D Left+

Class D Left-

Digital PWM

controller

VDD_PLL3

VDD_PLL1 VDD_PLSS

vol

BTL

Charge-Pump

Internal Audio Clock(s)

MCLK

PLL

Digital

Volume

Anti-

pop

DAC Left

DAC

HP Out Left

Vref

I2C_SDA

I2C_SCL

HP_DET

TEST

AFILT1

AFILT2

Control

Digital

Volume

Anti-

pop

DAC Right

DAC

HP Out Right

Audio Processing

Bass/Treble Enhancement

SYSTEM EQ

DAC Left

DACBCLK

DACLRCLK

DACIN

Class D Right+

Class D Right-

SPEAKER EQ

3-D effect

Compressor-limiter

Dynamic Range Expander

Digital PWM

controller

vol

BTL

LIN1

DAC Right

LIN2

D2S

RIN1

RIN2

ADCOUT

ADCLRCLK

ADCBCLK

-97 to +30 dB

In 0.5 dB steps

AGND

LIN1

MIC Bias

-17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB

Vref

LIN2

LIN3

D2S

Audio

Processing

VOL

AGC

Boost

mute

ADCL

LIN1

LIN2

-97 to +30 dB

In 0.5 dB steps

Automatic Level Control

LIN3/DMIC_CLK*

RIN1

RIN2

RIN3

D2S

Audio

Processing

VOL

AGC

Boost

mute

ADCR

RIN1

-17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB

RIN2

RIN3/DMIC_DAT*

*Digital Microphone Products

VSS_PLSS

VSS_XTAL

PVSS

DVSS

AVSS

CPGND

Figure 1. ACS422x68 TLA Block Diagram

V1.7 07/13

ACS422X68

1...5 6 789 10 11...93

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