ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
LIST OF FIGURES
Figure 1. ACS422x68 TLA Block Diagram .......................................................................................................8
Figure 2. ACS422x68 HLA Block Diagram ......................................................................................................9
Figure 3. Output Audio Processing ................................................................................................................13
Figure 4. Prescaler & EQ Filters ....................................................................................................................16
Figure 5. 6-Tap IIR Equalizer Filter ................................................................................................................16
Figure 6. DAC Coefficient RAM Write Sequence ...........................................................................................18
Figure 7. DAC Coefficient RAM Read Sequence ...........................................................................................19
Figure 8. Gain Compressor, Output vs Input .................................................................................................22
Figure 9. Compressor block diagram .............................................................................................................24
Figure 10. 3-D Channel Inversion ..................................................................................................................30
Figure 11. Bass Enhancement .......................................................................................................................30
Figure 12. Treble Enhancement ....................................................................................................................31
Figure 13. Interpolation and Filtering .............................................................................................................33
Figure 14. Constant Output Power Error ........................................................................................................37
Figure 15. Constant Output Power nominal and high/low ..............................................................................37
Figure 16. Temp sense volume adjustment algorithm ...................................................................................44
Figure 17. Input Audio Processing .................................................................................................................48
Figure 18. Mic Bias ........................................................................................................................................51
Figure 19. ADC Filter Data path .....................................................................................................................52
Figure 20. ADC Input processing ...................................................................................................................53
Figure 21. ALC Operation ..............................................................................................................................55
Figure 22. Single Digital Microphone (data is ported to both left and right channels) ....................................60
Figure 23. Stereo Digital Microphone Configuration ......................................................................................61
Figure 24. Master mode .................................................................................................................................62
Figure 25. Slave mode ...................................................................................................................................62
Figure 26. Left Justified Audio Interface (assuming n-bit word length) ..........................................................63
Figure 27. Right Justified Audio Interface (assuming n-bit word length) ........................................................63
Figure 28. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................64
Figure 29. Bit Clock mode ..............................................................................................................................68
Figure 30. 2-Wire Serial Control Interface ......................................................................................................69
Figure 31. Multiple Write Cycle ......................................................................................................................69
Figure 32. Read Cycle ...................................................................................................................................70
Figure 33. Multiple Read Cycle ......................................................................................................................70
Figure 34. ACS422x68TAG Pinout ................................................................................................................81
Figure 35. ......................................................................................................................................................82
Figure 36. ACS422x68NAG Pinout ................................................................................................................83
Figure 37. ......................................................................................................................................................84
Figure 38. Package Outline ...........................................................................................................................90
Figure 39. NAG/HLA Package Outline ...........................................................................................................91
5
V1.7 07/13
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
ACS422X68
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