ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
4.5.1. ADC Signal Path Control Register .....................................................................................54
4.5.2. ADC High Pass Filter Enable modes .................................................................................54
4.6. Digital ADC Volume Control .............................................................................................................54
4.6.1. ADC Digital Registers ........................................................................................................55
4.7. Automatic Level Control (ALC) ........................................................................................................55
4.7.1. ALC Operation ..................................................................................................................55
4.7.2. ALC Registers ....................................................................................................................57
4.7.3. Peak Limiter .......................................................................................................................58
4.7.4. Input Threshold ..................................................................................................................58
4.8. Digital Microphone Support .............................................................................................................58
4.8.1. DMIC Register ...................................................................................................................61
5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 62
5.1. Data Interface ..................................................................................................................................62
5.2. Master and Slave Mode Operation ..................................................................................................62
5.3. Audio Data Formats .........................................................................................................................63
5.4. Left Justified Audio Interface ...........................................................................................................63
5.5. Right Justified Audio Interface (assuming n-bit word length) ...........................................................63
5.6. I2S Format Audio Interface ..............................................................................................................64
5.7. Data Interface Registers ..................................................................................................................64
5.7.1. Audio Data Format Control Register ..................................................................................64
5.7.2. Audio Interface Output Tri-state .........................................................................................65
5.7.3. Audio Interface Bit Clock and LR Clock configuration ........................................................65
5.7.4. Bit Clock and LR Clock Mode Selection ............................................................................66
5.7.5. ADC Output Pin State ........................................................................................................67
5.7.6. Audio Interface Control 3 Register .....................................................................................67
5.8. Bit Clock Mode .................................................................................................................................67
5.9. Control Interface ..............................................................................................................................68
5.9.1. Register Write Cycle ..........................................................................................................68
5.9.2. Multiple Write Cycle ...........................................................................................................69
5.9.3. Register Read Cycle ..........................................................................................................69
5.9.4. Multiple Read Cycle ...........................................................................................................70
5.9.5. Device Addressing and Identification .................................................................................70
6. AUDIO CLOCK GENERATION ............................................................................................... 72
6.1. Internal Clock Generation (ACLK) ...................................................................................................72
6.1.1. External MCLK ...................................................................................................................72
6.2. ACLK Clocking and Sample Rates ..................................................................................................72
6.3. DAC/ADC Modulator Rate Control ...................................................................................................73
7. CHARACTERISTICS ............................................................................................................... 75
7.1. Electrical Specifications ...................................................................................................................75
7.1.1. Absolute Maximum Ratings ...............................................................................................75
7.1.2. Recommended Operating Conditions ................................................................................75
7.2. Device Characteristics .....................................................................................................................76
7.3. PLL Electrical Characteristics ..........................................................................................................78
8. REGISTER MAP ...................................................................................................................... 79
9. PIN INFORMATION ................................................................................................................. 81
9.1. ACS422x68TAG Pin Diagram ..........................................................................................................81
9.2. ACS422x68NAG Pin Diagram .........................................................................................................83
9.3. ACS422x68TAG Pin Tables ............................................................................................................85
9.3.1. ACS422x68TAG Power Pins .............................................................................................85
9.3.2. ACS422x68TAG Reference Pins .......................................................................................85
9.3.3. ACS422x68TAG Analog Input Pins ...................................................................................86
9.3.4. ACS422x68TAG Analog Output Pins ................................................................................86
9.3.5. ACS422x68TAG Data and Control Pins ............................................................................86
9.3.6. ACS422x68TAG Clock Pins ..............................................................................................87
9.4. ACS422x68NAG Pin Tables ............................................................................................................87
9.4.1. ACS422x68NAG Power Pins .............................................................................................87
9.4.2. ACS422x68NAG Reference Pins ......................................................................................88
9.4.3. ACS422x68NAG Analog Input Pins ...................................................................................88
9.4.4. ACS422x68NAG Analog Output Pins ................................................................................88
3
V1.7 07/13
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
ACS422X68
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