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ACS175K/SAMPLE-03 PDF预览

ACS175K/SAMPLE-03

更新时间: 2024-11-06 03:34:11
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
2页 41K
描述
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, DFP-16

ACS175K/SAMPLE-03 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:AC
JESD-30 代码:R-CDFP-F16逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:16输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:2.92 mm表面贴装:YES
技术:CMOS端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:6.73 mm
Base Number Matches:1

ACS175K/SAMPLE-03 数据手册

 浏览型号ACS175K/SAMPLE-03的Datasheet PDF文件第2页 
ACS175MS  
Data Sheet  
July 1999  
File Number 4763  
Radiation Hardened Quad D-Type Flip-  
Flop with Reset  
Features  
• QML Qualified Per MIL-PRF-38535 Requirements  
• 1.25 Micron Radiation Hardened SOS CMOS  
The Radiation Hardened ACS175MS is a Quad D-Type  
Flip-Flop with Reset. Information at the D input is  
• Radiation Environment  
transferred to the Q and Q outputs on the positive-going  
transition of the clock. All four flip-flops are controlled by a  
common clock (CP) and a common reset (MR). Resetting is  
accomplished by a LOW level independent of the clock. All  
inputs are buffered and the outputs are designed for  
balanced propagation delay and transition times.  
- Latch-Up Free Under Any Conditions  
5
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10 RAD(Si)  
-10  
- SEU Immunity. . . . . . . . . . . . . <1 x 10  
Errors/Bit/Day  
2
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm )  
• Input Logic Levels. . . . V = (0.3)(V ), V = (0.7)(V  
IL CC IH  
)
CC  
The ACS175MS is fabricated on a CMOS Silicon on  
Sapphire (SOS) process, which provides an immunity to  
Single Event Latch-up and the capability of highly reliable  
performance in any radiation environment. These devices  
offer significant power reduction and faster performance  
when compared to ALSTTL types.  
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)  
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)  
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .22ns (Max)  
Applications  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed below must be used when ordering.  
• High Speed Control Circuits  
• Sensor Monitoring  
• Low Power Designs  
Detailed Electrical Specifications for the ACS175MS are  
contained in SMD 5962-98635. A “hot-link” is provided  
on our homepage for downloading.  
http://www.intersil.com/spacedefense/spaceselect.htm  
Ordering Information  
INTERNAL MARKETING  
o
ORDERING NUMBER  
5962F9863501VCC  
NUMBER  
TEMP. RANGE ( C)  
PACKAGE  
16 Ld SBDIP  
DESIGNATOR  
CDIP2-T16  
CDIP2-T16  
CDFP4-F16  
CDFP4-F16  
NA  
ACS175DMSR-03  
-55 to 125  
ACS175D/SAMPLE-03  
5962F9863501VXC  
ACS175K/SAMPLE-03  
5962F9863501V9A  
ACS175D/SAMPLE-03  
ACS175KMSR-03  
25  
-55 to 125  
25  
16 Ld SBDIP  
16 Ld Flatpack  
16 Ld Flatpack  
Die  
ACS175K/SAMPLE-03  
ACS175HMSR-03  
25  
Pinouts  
ACS175MS  
ACS175MS  
(SBDIP)  
(FLATPACK)  
TOP VIEW  
TOP VIEW  
MR  
Q0  
1
2
3
4
5
6
7
8
16 V  
CC  
MR  
Q0  
1
2
3
4
5
6
7
8
16  
V
CC  
15 Q3  
14 Q3  
13 D3  
12 D2  
11 Q2  
10 Q2  
15  
14  
13  
12  
11  
10  
9
Q3  
Q3  
D3  
D2  
Q2  
Q2  
CP  
Q0  
Q0  
D0  
D0  
D1  
D1  
Q1  
Q1  
Q1  
Q1  
GND  
9
CP  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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