A89503
80 V Automotive Half-Bridge MOSFET Driver
LAYOUT RECOMMENDATIONS
Careful consideration must be given to PCB layout when design-
ing high-frequency, fast-switching, high-current circuits:
GND as close to the A89503 terminals as possible.
• Check the pick voltage excrusion of the transients on the LSS
terminal with reference to the GND terminal using a close-
grounded (‘tip & barrel’) probe. If the voltage at any LSS
terminal exceeds the absolute maximum in the datasheet,
add additional clamping and/or capacitance between the LSS
terminal and the GND terminal.
• The exposed thermal pad should be connected to the GND
terminal.
• Minimize stray inductance by using short, wide copper tracks
at the drain and source terminals of all power MOSFETs. This
includes load lead connections and the input power bus. This
will minimize voltages induced by fast switching of large load
currents.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore the traces from
GH, GL, S, and LSS should be as short as possible to reduce
the track indictance.
• Consider the addition of small (100 nF) ceramic decoupling
capacitor across the source and drain of the power MOSFETs
to limit fast transient voltage spikes caused by track
inductance.
• Provide an independent connection between the LSS terminal
to the source of the low-side MOSFET in the power bridge.
Connection of the LSS terminal directly to the GND terminal
is not recommended as this may inject noise into sensitive
functions such as the various voltage monitors.
• Keep the gate discharge return connections S and LSS as short
as possible. Any inductance on these tracks will cause negative
transitions on the corresponding A89503 terminals, which may
exceed the absolute maximum ratings. If this is likely, consider
the use of clamping diodes to limit the negative excursion on
these terminals with respect to the GND terminal.
• A low-cost diode can be placed in the connection to VBB
to provide reverse battery protection. In reverse battery
conditions, it is possible to use the body diodes of the power
MOSFETs to clamp the reverse voltage to approximately
4 V. In this case, the additional diode in the VBB connection
will prevent damage to the A89503 and the VBRG input will
survive the reverse voltage.
• Supply decoupling, typically a 100 nF ceramic capacitor,
should be connected between VBB and GND as close to the
A89503 terminals as possible.
• Supply decoupling should be connected between VREG and
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Figure 10: Supply Routing Suggestions
43
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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