Datasheet > A54SX72AFG484

A54SX72AFG484

更新时间： 2024-10-29 03:06:11

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
108页	793K
描述
Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA484

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A54SX72AFG484 数据手册

v5.3

™

SX-A Family FPGAs

•

Configurable I/O Support for 3.3 V / 5 V PCI, 5 V

TTL, 3.3 V LVTTL, 2.5 V LVCMOS2

2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Devices Support Multiple Temperature Grades

Configurable Weak-Resistor Pull-Up or Pull-Down

for I/O at Power-Up

Individual Output Slew Rate Control

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Leading-Edge Performance

•

250 MHz System Performance

350 MHz Internal Performance

•

Specifications

•

12,000 to 108,000 Available System Gates

Up to 360 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

•

0.22 μ / 0.25 μ CMOS Process Technology

Features

•

Boundary-Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and

Design Theft

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (No Sequencing Required

for Supply Voltages)

•

66 MHz PCI Compliant

Nonvolatile, Single-Chip Solution

Table 1 • SX-A Product Profile

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

32,000

48,000

72,000

108,000

Logic Modules

768

512

1,452

924

528

2,880

1,800

1,080

1,980

6,036

4,024

2,012

4,024

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

256

512 ¹

990

Maximum User I/Os

Global Clocks

130

180

249

360

Quadrant Clocks

Boundary Scan Testing

3.3 V / 5 V PCI

Yes

Input Set-Up (External)

Speed Grades²

0 ns

–F, Std, –1, –2

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

Temperature Grades

Package (by pin count)

PQFP

TQFP

PBGA

FBGA

CQFP

208

100, 144, 176

329

144, 256, 484

208, 256

208

100, 144

–

144

–

144, 256

–

256, 484

208, 256

Notes:

1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.

2. All –3 speed grades have been discontinued.

February 2007

See the Actel website for the latest version of the datasheet.

12 3 4 5 6 7...108

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与A54SX72AFG484相关器件

型号	品牌	获取价格	描述	数据表
A54SX72AFG484A	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA484,
A54SX72AFG484I	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA484,
A54SX72AFG484M	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA484,
A54SX72A-FGG208A	ACTEL	获取价格	SX-A Automotive Family FPGAs
A54SX72AFGG256	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA256,
A54SX72A-FGG256	MICROSEMI	获取价格	FPGA, 6036 CLBS, 108000 GATES, PBGA256, 1 MM, FBGA-256
A54SX72AFGG256A	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA256,
A54SX72AFGG256I	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA256,
A54SX72A-FGG256I	MICROSEMI	获取价格	FPGA, 6036 CLBS, 108000 GATES, PBGA256, 1 MM, FBGA-256
A54SX72AFGG256M	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 217MHz, 6036-Cell, CMOS, PBGA256,

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