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A54SX72A-1PQG208M PDF预览

A54SX72A-1PQG208M

更新时间: 2024-10-27 17:49:27
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
108页 716K
描述
Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 250MHz, 6036-Cell, CMOS, PQFP208, PLASTIC, ROHS COMPLIANT, QFP-208

A54SX72A-1PQG208M 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:FQFP, QFP208,1.2SQ,20Reach Compliance Code:compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.29其他特性:72000 TYPICAL GATES AVAILABLE
最大时钟频率:250 MHzCLB-Max的组合延迟:1.3 ns
JESD-30 代码:S-PQFP-G208长度:28 mm
湿度敏感等级:3可配置逻辑块数量:6036
等效关口数量:108000输入次数:171
逻辑单元数量:6036输出次数:171
端子数量:208最高工作温度:125 °C
最低工作温度:-55 °C组织:6036 CLBS, 108000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):245
电源:2.5,3.3/5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:4.1 mm
子类别:Field Programmable Gate Arrays最大供电电压:2.75 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:28 mm
Base Number Matches:1

A54SX72A-1PQG208M 数据手册

 浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第2页浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第3页浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第4页浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第5页浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第6页浏览型号A54SX72A-1PQG208M的Datasheet PDF文件第7页 
v5.3  
SX-A Family FPGAs  
u
e
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V  
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2  
2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with  
5 V Input Tolerance and 5 V Drive Strength  
Devices Support Multiple Temperature Grades  
Configurable Weak-Resistor Pull-Up or Pull-Down  
for I/O at Power-Up  
Individual Output Slew Rate Control  
Up to 100% Resource Utilization and 100% Pin  
Locking  
Deterministic, User-Controllable Timing  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer II  
Leading-Edge Performance  
250 MHz System Performance  
350 MHz Internal Performance  
Specifications  
12,000 to 108,000 Available System Gates  
Up to 360 User-Programmable I/O Pins  
Up to 2,012 Dedicated Flip-Flops  
0.22 μ / 0.25 μ CMOS Process Technology  
Features  
Boundary-Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
Actel Secure Programming Technology with  
FuseLock™ Prevents Reverse Engineering and  
Design Theft  
Hot-Swap Compliant I/Os  
Power-Up/Down Friendly (No Sequencing Required  
for Supply Voltages)  
66 MHz PCI Compliant  
Nonvolatile, Single-Chip Solution  
Table 1 SX-A Product Profile  
Device  
A54SX08A  
A54SX16A  
A54SX32A  
A54SX72A  
Capacity  
Typical Gates  
System Gates  
8,000  
12,000  
16,000  
24,000  
32,000  
48,000  
72,000  
108,000  
Logic Modules  
768  
512  
1,452  
924  
528  
2,880  
1,800  
1,080  
1,980  
6,036  
4,024  
2,012  
4,024  
Combinatorial Cells  
Dedicated Flip-Flops  
Maximum Flip-Flops  
256  
512 1  
990  
Maximum User I/Os  
Global Clocks  
130  
180  
249  
360  
3
3
3
3
Quadrant Clocks  
Boundary Scan Testing  
3.3 V / 5 V PCI  
0
Yes  
0
Yes  
0
Yes  
4
Yes  
Yes  
Yes  
Yes  
Yes  
Input Set-Up (External)  
Speed Grades2  
0 ns  
0 ns  
0 ns  
0 ns  
F, Std, –1, –2  
C, I, A, M  
F, Std, –1, –2, –3  
C, I, A, M  
F, Std, –1, –2, –3  
C, I, A, M  
F, Std, –1, –2, –3  
C, I, A, M  
Temperature Grades  
Package (by pin count)  
PQFP  
TQFP  
PBGA  
FBGA  
CQFP  
208  
208  
208  
100, 144, 176  
329  
144, 256, 484  
208, 256  
208  
100, 144  
100, 144  
144  
144, 256  
256, 484  
208, 256  
Notes:  
1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.  
2. All –3 speed grades have been discontinued.  
February 2007  
i
© 2007 Actel Corporation  
See the Actel website for the latest version of the datasheet.  
 
 

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