Datasheet > A54SX72A-2FG208M

A54SX72A-2FG208M

更新时间： 2024-10-27 22:38:43

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
108页	720K
描述
SX-A Family FPGAs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

A54SX72A-2FG208M 数据手册

v5.1

™

SX-A Family FPGAs

•

Configurable I/O Support for 3.3 V / 5 V PCI, 5 V

TTL, 3.3 V LVTTL, 2.5 V LVCMOS2

2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Devices Support Multiple Temperature Grades

Configurable Weak-Resistor Pull-Up or Pull-Down

for I/O at Power-Up

Individual Output Slew Rate Control

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Leading-Edge Performance

•

250 MHz System Performance

350 MHz Internal Performance

•

Specifications

•

12,000 to 108,000 Available System Gates

Up to 360 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

•

0.22 µ / 0.25 µ CMOS Process Technology

Features

•

Boundary-Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and

Design Theft

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (No Sequencing Required

for Supply Voltages)

•

66 MHz PCI Compliant

Nonvolatile, Single-Chip Solution

Table 1 • SX-A Product Profile

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

32,000

48,000

72,000

108,000

Logic Modules

768

512

256

1,452

924

528

2,880

1,800

1,080

1,980

6,036

4,024

2,012

4,024

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

512*

990

Maximum User I/Os

Global Clocks

130

180

249

360

Quadrant Clocks

Boundary Scan Testing

3.3 V / 5 V PCI

Yes

Input Set-Up (External)

Speed Grades

0 ns

–F, Std, –1, –2

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

Temperature Grades

Package (by pin count)

PQFP

TQFP

PBGA

FBGA

CQFP

208

100, 144, 176

329

144, 256, 484

208, 256

208

100, 144

–

144

–

144, 256

–

256, 484

208, 256

Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers

February 2005

See the Actel website for the latest version of the datasheet.

12 3 4 5 6 7...108

中文翻译

下载PDF

与A54SX72A-2FG208M相关器件

型号	品牌	获取价格	描述	数据表
A54SX72A-2FG256	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA256,
A54SX72A-2FG256I	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA256,
A54SX72A-2FG256IX79	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, CMOS, PBGA256, 1 MM PITCH,
A54SX72A-2FG256X79	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, CMOS, PBGA256, 1 MM PITCH,
A54SX72A-2FG484	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA484
A54SX72A-2FG484I	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA484
A54SX72A-2FG484IX79	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, CMOS, PBGA484
A54SX72A-2FG484X79	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, CMOS, PBGA484, 1 MM PITCH,
A54SX72A-2FGG256	MICROSEMI	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA256,
A54SX72A-2FGG256I	ACTEL	获取价格	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 294MHz, 6036-Cell, CMOS, PBGA256,

与A54SX72A-2FG208M相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

12
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

11
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

38
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

46

产品中心

服务支持

精选活动

关于我们

帮助中心

A54SX72A-2FG208M

A54SX72A-2FG208M 数据手册

与A54SX72A-2FG208M相关器件

与A54SX72A-2FG208M相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

A54SX72A-2FG208M

A54SX72A-2FG208M 数据手册

与A54SX72A-2FG208M相关器件

与A54SX72A-2FG208M相关文章

您还可以找

您在本页遇到什么问题？