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A54SX72A-1PQ208AX79 PDF预览

A54SX72A-1PQ208AX79

更新时间: 2024-10-27 15:35:55
品牌 Logo 应用领域
美高森美 - MICROSEMI 可编程逻辑
页数 文件大小 规格书
83页 2107K
描述
Field Programmable Gate Array, 6036-Cell, CMOS, PQFP208,

A54SX72A-1PQ208AX79 数据手册

 浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第2页浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第3页浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第4页浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第5页浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第6页浏览型号A54SX72A-1PQ208AX79的Datasheet PDF文件第7页 
v 4 . 0  
SX-A Family FPGAs  
u
e
L e a d i n g -E d g e P e r f o r m a n c e  
• 250 MHz System Performance  
• 350 MHz Internal Performance  
• 3.8 ns Clock-to-Out (Pad-to-Pad)  
Configurable I/O Support for 3.3V/5V PCI, 5V TTL,  
3.3V LVTTL, 2.5V LVCMOS2  
• 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input  
Tolerance and 5V Drive Strength  
S p e c i f i c a t i o n s  
• 12,000 to 108,000 Available System Gates  
Up to 360 User-Programmable I/O Pins  
Devices Support Multiple Temperature Grades  
Configurable Weak-Resistor Pull-up or Pull-down for  
Outputs at Power-up  
Up to 2,012 Dedicated Flip-Flops  
• Individual Output Slew Rate Control  
• 0.22µ/0.25µ CMOS Process Technology  
Up to 100% Resource Utilization and 100% Pin Locking  
Deterministic, User-Controllable Timing  
F e a t u r e s  
Hot-Swap Compliant I/Os  
Unique In-System Diagnostic and Verification Capability  
with Silicon Explorer II  
• Power-up/down Friendly (No Sequencing Required for  
Supply Voltages)  
Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
• 66 MHz PCI Compliant  
• Single-Chip Solution  
Nonvolatile  
Actels Secure Programming Technology with FuseLock™  
Prevents Reverse Engineering and Design Theft  
S X -A P r o d u c t P r o f i l e  
Device  
A54SX08A  
A54SX16A  
A54SX32A  
A54SX72A  
Capacity  
Typical Gates  
System Gates  
8,000  
12,000  
16,000  
24,000  
32,000  
48,000  
72,000  
108,000  
Logic Modules  
Combinatorial Cells  
768  
512  
1,452  
924  
2,880  
1,800  
6,036  
4,024  
Register Cells  
Dedicated Flip-Flops  
Maximum Flip-Flops  
256  
512  
528  
990  
1,080  
1,980  
2,012  
4,024  
Maximum User I/Os  
Global Clocks  
130  
3
180  
3
249  
3
360  
3
Quadrant Clocks  
Boundary Scan Testing  
3.3V/5V PCI  
0
0
0
4
Yes  
Yes  
4.2 ns  
0 ns  
Yes  
Yes  
4.6 ns  
0 ns  
Yes  
Yes  
4.7 ns  
0 ns  
Yes  
Yes  
5.8 ns  
0 ns  
Clock-to-Out  
Input Set-Up (External)  
Speed Grades  
F, Std, –1, –2, –3 F, Std, –1, –2, –3 F, Std, –1, –2, –3 F, Std, –1, –2, –3  
Temperature Grades  
C, I, A  
C, I, M, A  
C, I, M, A  
C, I, M, A  
Package (by pin count)  
PQFP  
TQFP  
PBGA  
FBGA  
CQFP*  
208  
100, 144  
208  
100, 144  
208  
100, 144, 176  
329  
144, 256, 484  
208, 256  
208  
144  
144, 256  
256, 484  
208, 256  
Note: For more information about the CQFP package options, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf  
A p r i l 2 0 0 3  
1
© 2001 Actel Corporation  

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