Datasheet > 存储 > DRAM> A43P26161V-75UF

A43P26161V-75UF

更新时间： 2024-02-07 15:40:46

品牌	Logo	应用领域
联笙电子 - AMICC		存储动态存储器
页数	文件大小	规格书
44页	1122K
描述
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

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技术参数
数据手册

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A43P26161V-75UF 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

A43P26161V-75UF 数据手册

A43P26161

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

Unit

Note

-75

-95

tRRD(min)

tRCD(min)

Row active to row active delay

CLK

RAS to

delay

CAS

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row precharge time

Row active time

µs

100

Row cycle time

tCDL(min)

tRDL(min)

tBDL(min)

tCCD(min)

Last data in new col. Address delay

Last data in row precharge

7.5

9.5

CLK

1, 2

Last data in to burst stop

7.5

9.5

Col. Address to col. Address delay

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

PRELIMINARY (July, 2005, Version 1.1)

AMIC Technology, Corp.

1...5 6 789 10 11...44

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