Datasheet > 存储 > DRAM> A43P26161V-75UF

A43P26161V-75UF

更新时间： 2024-02-17 00:10:10

品牌	Logo	应用领域
联笙电子 - AMICC		存储动态存储器
页数	文件大小	规格书
44页	1122K
描述
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

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技术参数
数据手册

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A43P26161V-75UF 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

A43P26161V-75UF 数据手册

A43P26161

Mode Register Filed Table to Program Modes

Address

BS1

BS0

A11,A10

Function

RFU

W.B.L

CAS Latency

Burst Length

(Note 3)

(Note 1)

(Note 2)

Test Mode

Type

CAS Latency

A6 A5 A4 Latency

Burst Type

Burst Length

A8 A7

Type

A2 A1 A0

BT=0

BT=1

Mode Register Set

Reserved

Sequential

Interleave

Vendor

Use

Only

Reserved

Reserved Reserved

256(Full) Reserved

Write Burst Length

Length

Burst

Single Bit

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. BS0, BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register).

Extended Mode Register Table

BS1

BS0 A11, A10

Address Bus (Ax)

↓

TCSR

↓

PASR

↓

All have to be set to “0”

(Note)

Driver Strength

Temperature-Compensated Self-Refresh:

Partial-Array Self Refresh:

Driver Strength

Max. Case Temp.

Banks to be Self-Refreshed

70°C

45°C

15°C

85°C

A6 A5 Driver Strength

Full

1/2

1/4

All banks

Bank A, Bank B

Bank A

Reserved

1/2 of Bank A

1/4 of Bank A

Reserved

Note: BS1 and BS0 must be 1, 0 to select the Extended Mode Register (vs. the Mode Register)

PRELIMINARY (July, 2005, Version 1.1)

AMIC Technology, Corp.

1...7 8 91011 12 13...44

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