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A43E16161G-75UF PDF预览

A43E16161G-75UF

更新时间: 2024-02-16 09:50:53
品牌 Logo 应用领域
联笙电子 - AMICC 时钟动态存储器内存集成电路
页数 文件大小 规格书
48页 557K
描述
Synchronous DRAM, 2MX16, 6ns, CMOS, PBGA54

A43E16161G-75UF 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:FBGA, BGA54,9X9,32Reach Compliance Code:unknown
风险等级:5.75最长访问时间:6 ns
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:S-PBGA-B54
内存密度:33554432 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16端子数量:54
字数:2097152 words字数代码:2000000
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA54,9X9,32封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH电源:1.8 V
认证状态:Not Qualified刷新周期:4096
连续突发长度:1,2,4,8,FP最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.06 mA
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

A43E16161G-75UF 数据手册

 浏览型号A43E16161G-75UF的Datasheet PDF文件第7页浏览型号A43E16161G-75UF的Datasheet PDF文件第8页浏览型号A43E16161G-75UF的Datasheet PDF文件第9页浏览型号A43E16161G-75UF的Datasheet PDF文件第11页浏览型号A43E16161G-75UF的Datasheet PDF文件第12页浏览型号A43E16161G-75UF的Datasheet PDF文件第13页 
A43E16161  
Mode Register Filed Table to Program Modes  
Register Programmed with MRS  
Address  
BA  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Function  
0
RFU  
W.B.L  
TM  
CAS Latency  
BT  
Burst Length  
(Note 3)  
(Note 1)  
(Note 2)  
Test Mode  
Type  
CAS Latency  
Burst Type  
Burst Length  
A8 A7  
A6 A5 A4  
Latency  
A3  
Type  
A2 A1 A0  
BT=0  
BT=1  
0
0
1
0
1
0
Mode Register Set  
0
0
0
0
0
1
0
1
0
Reserved  
0
1
Sequential  
Interleave  
0
0
0
0
0
1
0
1
0
1
2
4
1
2
4
Vendor  
Use  
-
2
Only  
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
8
8
Reserved  
Reserved  
Reserved  
Reserved  
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
512(Full) Reserved  
Write Burst Length  
Length  
A9  
0
Burst  
1
Single Bit  
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.  
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.  
3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register).  
Extended Mode Register Table  
BA  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Address Bus (Ax)  
1
Bank  
PASR  
All have to be set to “0”  
DS  
0
Up/Down  
(Note)  
Driver Strength  
Partial-Array Self Refresh:  
Driver Strength  
A7  
A2  
A1  
A0  
Banks to be Self-Refreshed  
A6  
A5  
Driver Strength  
0
0
1
1
0
1
0
1
Full  
3/4  
1/2  
1/4  
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
X
0
0
1
1
X
0
1
0
1
X
0
1
0
1
X
All banks (Bank 0, 1)  
Reserved  
Bank 0  
Reserved  
Reserved  
All banks (Bank 0, 1)  
Reserved  
One bank (Bank 1)  
Reserved  
Reserved  
Note: BA must be 1 to select the Extended Mode Register (vs. the Mode Register)  
PRELIMINARY (February, 2008, Version 0.3)  
9
AMIC Technology, Corp.  

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