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A3PE1500-FFGG484I

更新时间： 2024-11-10 14:47:31
品牌 Logo 应用领域
ACTEL 栅可编程逻辑
页数 文件大小 规格书
168页 1335K
描述
Field Programmable Gate Array, 1500000 Gates, CMOS, PBGA484, 1 MM PITCH, GREEN, FBGA-484

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A3PE1500-FFGG484I 技术参数

是否Rohs认证：符合生命周期：Transferred
包装说明：1 MM PITCH, GREEN, FBGA-484Reach Compliance Code：compliant
风险等级：5.76Is Samacsys：N
JESD-30 代码：S-PBGA-B484JESD-609代码：e1
长度：23 mm湿度敏感等级：3
等效关口数量：1500000端子数量：484
最高工作温度：85 °C最低工作温度：-40 °C
组织：1500000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：250
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.44 mm最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：23 mmBase Number Matches：1

A3PE1500-FFGG484I 数据手册

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Advanced v0.5  
ProASIC3®E Flash Family FPGAs  
with Optional Soft ARM Support  
®
®
Pro (Professional) I/O  
Features and Benefits  
High Capacity  
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os  
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/  
2.5 V/1.8 V/1.5 V, 3.3 V PCI/3.3 V PCI-X, and LVCMOS  
2.5 V/5.0 V Input  
•
•
•
600 k to 3 Million System Gates  
108 k to 504 kbits of True Dual-Port SRAM  
Up to 616 User I/Os  
Reprogrammable Flash Technology  
•
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and  
M-LVDS  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Voltage-Referenced I/O Standards: GTL+ 2.5 V/3.3 V,  
GTL 2.5 V/3.3 V, HSTL Class I and II, SSTL2 Class I and II,  
SSTL3 Class I and II  
•
•
•
Live At Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
Retains Programmed Design When Powered Off  
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold Sparing I/Os  
On-Chip User Nonvolatile Memory  
Programmable Output Slew Rate and Drive Strength  
Programmable Input Delay  
•
1 kbit of FlashROM with Synchronous Interfacing  
Schmitt-Trigger Option on Single-Ended Inputs  
Weak Pull-Up/Down  
High Performance  
•
•
350 MHz System Performance  
3.3 V, 66 MHz 64-Bit PCI  
IEEE1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages Across the ProASIC3E Family  
In-System Programming (ISP) and Security  
Clock Conditioning Circuit (CCC) and PLL  
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE1532-  
compliant)  
•
•
Six CCC Blocks, Each with an Integrated PLL  
Flexible Phase-Shift, Multiply/Divide, and Delay  
Capabilities  
®
•
FlashLock to Secure FPGA Contents  
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)  
Low Power  
SRAMs and FIFOs  
•
•
•
1.5 V Core Voltage for Low Power  
Support for 1.5-V-Only Systems  
Low-Impedance Flash Switches  
•
Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4,  
x9, x18 Organizations Available)  
•
•
True Dual-Port SRAM (except x18)  
24 SRAM and FIFO Configurations with Synchronous  
Operation up to 350 MHz  
High-Performance Routing Hierarchy  
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
Ultra-Fast Local and Long-Line Network  
Enhanced High-Speed, Very-Long-Line Network  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
Soft ARM7™ Core Support in M7 ProASIC3E  
Devices  
•
CoreMP7Sd (with debug) and CoreMP7S (without debug)  
Table 1 •  
ProASIC3E Product Family  
ProASIC3E Devices  
A3PE600  
A3PE1500  
A3PE3000  
1
ARM-Enabled ProASIC3E Devices  
System Gates  
VersaTiles (D-Flip-Flops)  
RAM kbits (1,024 bits)  
4,608 Bit Blocks  
M7A3PE600  
M7A3PE1500  
M7A3PE3000  
600 k  
13,824  
108  
24  
1.5 M  
38,400  
270  
60  
3 M  
75,264  
504  
112  
1 k  
FlashROM Bits  
1 k  
1 k  
Secure (AES) ISP  
Yes  
Yes  
Yes  
2
6
6
6
CCCs with Integrated PLLs  
3
18  
18  
18  
VersaNet Globals  
I/O Banks  
8
8
8
Maximum User I/Os  
270  
439  
616  
Package Pins  
PQFP  
PQ208  
FG256, FG484  
PQ208  
FG484, FG676  
PQ208  
FG484, FG896  
FBGA  
Notes:  
1. Refer to the CoreMP7 datasheet for more information.  
2. The PQ208 package has six CCCs and two PLLs.  
3. Six chip (main) and three quadrant global networks are available.  
4. For devices supporting lower densities, refer to the ProASIC3 Flash FPGAs datasheet.  
April 2006  
i
© 2006 Actel Corporation  
See the Actel website for the latest version of the datasheet.  
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