Datasheet > A3P250L-FG256Y

A3P250L-FG256Y

更新时间： 2024-11-06 03:25:59

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
242页	11392K
描述
FPGA

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技术参数
数据手册

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A3P250L-FG256Y 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	BGA, BGA256,16X16,40	Reach Compliance Code：	unknown
风险等级：	5.28	最大时钟频率：	250 MHz
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
湿度敏感等级：	3	输入次数：	157
逻辑单元数量：	6144	输出次数：	157
端子数量：	256	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,16X16,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225	电源：	1.2/1.5,1.2/3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
子类别：	Field Programmable Gate Arrays	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	Base Number Matches：	1

A3P250L-FG256Y 数据手册

Revision 13

ProASIC3L Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

•

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os Programmable Output

Slew Rate and Drive Strength

Low Power

•

Dramatic Reduction in Dynamic and Static Power Savings

1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry to / Exit from Low-Power Flash*Freeze

Mode

•

Supports Single-Voltage System Operation

Low-Impedance Switches

High Capacity

•

250,000 to 3,000,000 System Gates

Up to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

•

Reprogrammable Flash Technology

•

Programmable Input Delay (A3PE3000L only)

Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

Weak Pull-Up/-Down

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

•

Instant On Level 0 Support

IEEE 1149.1 (JTAG) Boundary Scan Test

Single-Chip Solution

Retains Programmed Design when Powered Off

Pin-Compatible Packages across the ProASIC 3L Family

(except PQ208)

High Performance

Clock Conditioning Circuit (CCC) and PLL

•

350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

•

Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All

with Integrated PLL (ProASIC3EL)

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems))

•

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

SRAMs and FIFOs

•

FlashLock to Secure FPGA Contents

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

High-Performance Routing Hierarchy

•

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous

Operation:

•

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

– 250 MHz: For 1.2 V systems

Advanced and Pro (Professional) I/Os

– 350 MHz: For 1.5 V systems

•

700 Mbps DDR, LVDS-Capable I/Os

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

ARM^®Processor Support in ProASIC3L FPGAs

•

ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1 • ProASIC3 Low-Power Product Family

ProASIC3L Devices

A3P250L

A3P600L

A3P1000L

A3PE3000L

ARM Cortex-M1

Devices ¹

M1A3P600L

M1A3P1000L

M1A3PE3000L

System Gates

250,000

600,000

13,824

108

1,000,000

3,000,000

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

6,144

24,576

144

75,264

504

112

FlashROM Kbits

Secure (AES) ISP

Yes

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

157

235

300

620

Package Pins

VQFP

VQ100

PQ208

FG144, FG256

PQFP

PQ208

FG144, FG256, FG484

PQ208

FG144, FG256, FG484

PQ208

FBGA

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM Cortex-M1 ProASIC3L devices.

3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

January 2013

12 3 4 5 6 7...242

中文翻译

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与A3P250L-FG256Y相关器件

型号	品牌	获取价格	描述	数据表
A3P250L-FG256YI	MICROSEMI	获取价格	Field Programmable Gate Array, 250MHz, 6144-Cell, CMOS, PBGA256,
A3P250L-FGG144Y	MICROSEMI	获取价格	Field Programmable Gate Array, 250MHz, 6144-Cell, CMOS, PBGA144
A3P250L-FGG144YI	MICROSEMI	获取价格	FPGA
A3P250L-FGG256Y	MICROSEMI	获取价格	Field Programmable Gate Array, 250MHz, 6144-Cell, CMOS, PBGA256,
A3P250L-FGG256YI	MICROSEMI	获取价格	FPGA
A3P250L-PQ208Y	MICROSEMI	获取价格	FPGA
A3P250L-PQ208YI	MICROSEMI	获取价格	FPGA
A3P250L-PQG208Y	MICROSEMI	获取价格	FPGA
A3P250L-PQG208YI	MICROSEMI	获取价格	FPGA
A3P250L-VQ100I	MICROSEMI	获取价格	ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

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