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A3P250L-FGG144YI PDF预览

A3P250L-FGG144YI

更新时间: 2024-11-06 03:25:59
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美高森美 - MICROSEMI /
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242页 11392K
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FPGA

A3P250L-FGG144YI 数据手册

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Revision 13  
ProASIC3L Low Power Flash FPGAs  
with Flash*Freeze Technology  
Features and Benefits  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II (A3PE3000L only)  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os Programmable Output  
Slew Rate and Drive Strength  
Low Power  
Dramatic Reduction in Dynamic and Static Power Savings  
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power  
Low Power Consumption in Flash*Freeze Mode Allows for  
Instantaneous Entry to / Exit from Low-Power Flash*Freeze  
Mode  
Supports Single-Voltage System Operation  
Low-Impedance Switches  
High Capacity  
250,000 to 3,000,000 System Gates  
Up to 504 kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
Reprogrammable Flash Technology  
Programmable Input Delay (A3PE3000L only)  
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)  
Weak Pull-Up/-Down  
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Instant On Level 0 Support  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Single-Chip Solution  
Retains Programmed Design when Powered Off  
Pin-Compatible Packages across the ProASIC 3L Family  
(except PQ208)  
High Performance  
Clock Conditioning Circuit (CCC) and PLL  
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System  
Performance  
3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit  
PCI (1.2 V systems)  
Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All  
with Integrated PLL (ProASIC3EL)  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V  
systems) and 350 MHz (1.5 V systems))  
In-System Programming (ISP) and Security  
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
(AES) Decryption via JTAG (IEEE 1532–compliant)  
SRAMs and FIFOs  
®
FlashLock to Secure FPGA Contents  
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
High-Performance Routing Hierarchy  
True Dual-Port SRAM (except ×18)  
24 SRAM and FIFO Configurations with Synchronous  
Operation:  
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
– 250 MHz: For 1.2 V systems  
Advanced and Pro (Professional) I/Os  
– 350 MHz: For 1.5 V systems  
700 Mbps DDR, LVDS-Capable I/Os  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
ARM® Processor Support in ProASIC3L FPGAs  
ARM Cortex™-M1 Soft Processor Available with or without  
Debug  
Table 1 • ProASIC3 Low-Power Product Family  
ProASIC3L Devices  
A3P250L  
A3P600L  
A3P1000L  
A3PE3000L  
ARM Cortex-M1  
Devices 1  
M1A3P600L  
M1A3P1000L  
M1A3PE3000L  
System Gates  
250,000  
600,000  
13,824  
108  
24  
1,000,000  
3,000,000  
VersaTiles (D-flip-flops)  
RAM Kbits (1,024 bits)  
4,608-Bit Blocks  
6,144  
36  
8
24,576  
144  
32  
75,264  
504  
112  
1
FlashROM Kbits  
1
1
1
2
Secure (AES) ISP  
Yes  
1
Yes  
1
Yes  
1
Yes  
6
3
Integrated PLL in CCCs  
VersaNet Globals  
I/O Banks  
18  
4
18  
18  
18  
4
4
8
Maximum User I/Os  
157  
235  
300  
620  
Package Pins  
VQFP  
VQ100  
PQ208  
FG144, FG256  
3
PQFP  
PQ208  
FG144, FG256, FG484  
PQ208  
FG144, FG256, FG484  
PQ208  
FBGA  
FG324, FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.  
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.  
January 2013  
I
© 2013 Microsemi Corporation  

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