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A3985SLDTR-T PDF预览

A3985SLDTR-T

更新时间: 2024-02-19 01:03:12
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
15页 447K
描述
Digitally Programmable Dual Full-Bridge MOSFET Driver

A3985SLDTR-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:38
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.56
高边驱动器:YES接口集成电路类型:FULL BRIDGE BASED MOSFET DRIVER
JESD-30 代码:R-PDSO-G38JESD-609代码:e3
长度:9.7 mm湿度敏感等级:2
功能数量:1端子数量:38
最高工作温度:85 °C最低工作温度:-20 °C
标称输出峰值电流:0.2 A封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V电源电压1-最大:50 V
电源电压1-分钟:12 V表面贴装:YES
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

A3985SLDTR-T 数据手册

 浏览型号A3985SLDTR-T的Datasheet PDF文件第6页浏览型号A3985SLDTR-T的Datasheet PDF文件第7页浏览型号A3985SLDTR-T的Datasheet PDF文件第8页浏览型号A3985SLDTR-T的Datasheet PDF文件第10页浏览型号A3985SLDTR-T的Datasheet PDF文件第11页浏览型号A3985SLDTR-T的Datasheet PDF文件第12页 
Digitally Programmable  
Dual Full-Bridge MOSFET Driver  
A3985  
through the motor winding and the current sense resistor,  
blanking function The blank timer is reset when PHASE is  
changed.  
RSENSEx. When the voltage across RSENSEx equals the  
DAC output voltage, the current sense comparator resets  
the PWM latch, which turns off the source MOSFET (slow  
decay mode) or the sink and source MOSFETs (fast decay  
mode). The maximum value of current limiting is set by the  
selection of RSENSE and the voltage at the REF input, with a  
transconductance function approximated by:  
The blank time can be set to 4, 6, 8, or 12 periods of the mas-  
ter clock by programming the blank time bits in the Control  
register (Word1, Bits D1 and D2) using the serial port.  
Dead Time To prevent cross-conduction (shoot through)  
in the power full-bridge, a dead time, tDEAD , is introduced  
between switching one MOSFET off and switching the  
complementary MOSFET on. The dead time, tDEAD, is  
nominally half of tBLANK, but may be up to 1 cycle longer to  
synchronize with the master clock.  
ITrip(max) = VREF/(Gm × RSENSE) ,  
where Gm is the range factor defined by in the Data register  
(Word0: Bits D17 and D18).  
The DAC output reduces the VREF output to the current  
sense comparator, VDAC, in precise steps:  
Mixed Decay Operation  
Mixed decay is a technique that provides greater control  
of phase currents while the current is decreasing. When a  
stepper motor is driven at high speed, the back EMF from  
the motor will lag behind the driving current. If a passive  
current decay mode, such as slow decay, is used in the cur-  
rent control scheme, then the motor back EMF can cause the  
phase current to rise out of control. Mixed decay eliminates  
this effect by putting the full-bridge initially into fast decay,  
and then switching to slow decay after some time. Because  
fast decay is an active (driven) decay mode, this portion of  
the current decay cycle will ensure that the current remains  
in control. Using fast decay for the full current decay time  
(off-time, tOFF) would result in a large ripple current, but  
switching to slow decay once the current is in control will  
reduce the ripple current value. The portion of the off-time  
that the full-bridge has to remain in fast decay will depend  
on the characteristics and the speed of the motor.  
VDAC = [(1 + DAC) × VREF] / 64 ,  
where DAC is the decimal equivalent value of the Bridge  
DAC bits in the Data register (Word0: Bits D1 through D6  
for Bridge 1, Bits 9 through 14 for Bridge 2). (Active codes  
are represented by the values 1 through 63. Programming a  
DAC input code to 0 disables the corresponding bridge, and  
results in minimum load current.)  
The current trip level for each DAC value then becomes:  
ITripDAC = VDAC/(Gm × RSENSE) .  
PWM Timer Function All bridge control timing is based  
on the master clock. The PWM timer is programmed via the  
serial port to provide fixed off-time PWM signals to the con-  
trol block. The off-time, tOFF, is selected by programming  
the Off-Time bits in the Control register (Word1, Bits D3  
through D7) using the serial port. tOFF may be up to 1 cycle  
longer than the programmed value, to synchronize with the  
master clock.  
When the phase current is rising, the motor back EMF does  
not affect the current control, and slow decay may be used  
to minimize the phase current ripple. The A3985 must be  
programmed to switch between slow decay, when the cur-  
rent is rising, and mixed decay, when the current is falling.  
To simplify this programming sequence the decay mode is  
included in the data word (Word0) with the phase current trip  
level and the phase current direction.  
Blanking When a source driver is turned on, a current  
spike occurs due to the reverse-recovery currents of the  
clamp diodes and switching transients related to distributed  
capacitance in the load. To prevent false overcurrent detec-  
tion due to this current spike, the output from the current  
sense comparator is ignored (blanked) for a duration of time  
called the blank time. The blank timer runs, when a source  
power MOSFET is turned on, to provide the programmable  
When mixed decay is used, the portion of the off-time that  
the full-bridge remains in fast decay, tFD , is selected by pro-  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff, Box 15036  
9
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  

A3985SLDTR-T 替代型号

型号 品牌 替代类型 描述 数据表
A3985SLD-T ALLEGRO

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