Digitally Programmable
Dual Full-Bridge MOSFET Driver
A3985
is low. When the output swings high, the voltage on this ter-
minal rises with the output to provide the boosted gate volt-
age needed for the high-side N-channel power MOSFETs.
The bootstrap capacitor should be ceramic and have a value
of 10 to 20 times the total MOSFET gate capacitance.
SDI, SCK, STR, SDO These are the serial port interface
pins. Data is clocked into SDI by a clock signal on SCK.
The data is then latched by a signal on STR. If required, the
serial data out pin, SDO, can be used to read back the previ-
ously-latched serial data or to form a daisy chain for multiple
controllers using a single STR connection. (For bit assign-
ment details, see the Bit Assignments table.)
GH1A, GH1B, GH2A, and GH2B High-side gate drive
outputs for external N-channel MOSFETs. External series
gate resistors can be used to control the slew rate seen at
the gate, thereby controlling the di/dt and dv/dt at the motor
terminals. GHxx=1 (high) means that the upper half of the
driver is turned on and will source current to the gate of the
high-side MOSFET in the external motor-driving bridge.
GHxx= 0 (low) means that the lower half of the driver is
turned on and will sink current from the external MOSFET
gate circuit to the respective Sxx pin.
WC This input provides a lockout capability for writing
to the Control register. When set to logic high, no changes
can be made to the Control register through the serial port.
When at logic low, the data on the serial port will update the
Control register (if selected by D0 = 1) while STR is high.
This provides a mechanism to avoid inadvertently changing
the Control register settings by erroneous or corrupt serial
data signals.
S1A, S1B, S2A, and S2B Directly connected to the
motor, these terminals sense the voltages switched across the
load and define the negative supply for the floating high-side
drivers. The discharge current from the high-side MOSFET
gate capacitance flows through these connections which
should have low impedance traces to the MOSFET bridge.
Gate Drive
The A3985 is designed to drive external power N-chan-
nel MOSFETs. It supplies the transient currents necessary
to quickly charge and discharge the external FET gate
capacitance in order to reduce dissipation in the external
FET during switching. The charge and discharge rate can
be controlled using an external resistor, RGx, in series with
the connection to the gate of the FET. Cross-conduction is
prevented by the gate drive circuits which introduce a dead
time, tDEAD , between switching one FET off and the comple-
mentary FET on. tDEAD is at least 2, 3, 4, or 6 periods of the
master clock, depending on the corresponding value set in
the Control register (Word 1: bits D1 and D2). tDEAD can be
up to 1 cycle longer than the programmed value, to allow
synchronization with the master clock.
GL1A, GL1B, GL2A, and GL2B Low-side gate drive
outputs for external N-channel MOSFETs. External series
gate resistors (as close as possible to the MOSFET gate)
can be used to reduce the slew rate seen at the gate, thereby
controlling the di/dt and dv/dt at the motor terminals.
GLxx=1 (high) means that the upper half of the driver is
turned on and will source current to the gate of the low-side
MOSFET in the external motor-driving bridge. GLxx=0
(low) means that the lower half of the driver is turned on and
will sink current from the gate of the external MOSFET to
the LSSx pin.
ENABLE This input simply turns off all of the power MOS-
FETs. Set to logic high to disable outputs. When at logic low,
the internal control enables the outputs as required. Inputs to
the registers and the internal sequencing logic are all active
independent of the ENABLE input state.
LSS1 and LSS2 Low-side return path for discharge of the
gate capacitors, connected to the common sources of the
low-side external FETs through low-impedance traces.
Internal PWM Current Control
C1A, C1B, C2A, and C2B High-side connections for the
bootstrap capacitors, CBOOTx, and positive supply for high-
side gate drivers. The bootstrap capacitors are charged to
Each full-bridge is independently controlled by a fixed off-
time PWM current control circuit that limits the load current
in the phase to a desired value, ITrip. Initially, a diagonal pair
approximately VREG when the associated output Sxx terminal of source and sink MOSFETs are enabled and current flows
Allegro MicroSystems, Inc.
8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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