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A3938SLD PDF预览

A3938SLD

更新时间: 2024-02-09 15:00:50
品牌 Logo 应用领域
急速微 - ALLEGRO 运动控制电子器件信号电路光电二极管电动机控制控制器
页数 文件大小 规格书
11页 399K
描述
Three-Phase Power MOSFET Controller

A3938SLD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SSOP, SOP36,.4,32
针数:36Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73模拟集成电路 - 其他类型:BRUSHLESS DC MOTOR CONTROLLER
JESD-30 代码:R-PDSO-G36长度:15.3 mm
功能数量:1端子数量:36
最高工作温度:85 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SOP36,.4,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:18/50 V
认证状态:Not Qualified座面最大高度:2.64 mm
子类别:Motion Control Electronics最大供电电流 (Isup):8 mA
最大供电电压 (Vsup):50 V最小供电电压 (Vsup):18 V
表面贴装:YES温度等级:OTHER
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

A3938SLD 数据手册

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A3938  
Three-Phase Power MOSFET Controller  
each commutation. If a stalled motor results from a fault, the  
fault can only be cleared by toggling the RESET pin or by a  
power-up sequence.  
of the power MOSFETs. To prevent false tripping of the  
sense comparator, the BLANK function disables the com-  
parator for a time period dened by:  
Current Regulation. Load current can be regulated by  
an internal xed off-time, PWM-control circuit. When the  
outputs of the MOSFETs are turned on, current increases in  
the motor winding until it reaches a value given by:  
tBLANK = 1.9 C / (1 10-3 – [2 / R ])  
×
×
T
T
The user must ensure that CT is large enough to cover the  
current spike duration.  
Braking. The A3938 dynamically brakes the motor by  
forcing all low-side power MOSFETs on, and all high-side  
power MOSFETs off. This effectively short-circuits the  
BEMF and brakes the motor. During braking, the load cur-  
rent can be approximated by:  
ITRIP = VREF / RSENSE  
At the trip point, the sense comparator resets the source  
enable latch, turning off the source driver. At this point, load  
inductance causes the current to recirculate for the xed off-  
time period. The current path during recirculation is deter-  
mined by the conguration of the MODE and SR input pins.  
The xed off-time is determined by an external resistor, RT,  
and capacitor, CT, connected in parallel from the RC terminal  
to AGND. The xed off-time is approximated by:  
IBRAKEPEAK = VBEMF / RLOAD  
As the current does not ow through the sense resistor dur-  
ing a dynamic brake, care should be taken to ensure that the  
maximum ratings of the power MOSFETs are not exceeded.  
tOFF = R  
C
T
×
T
Note: On its rising edge, a RESET setting of 1 overrides the  
BRAKE input pin and latches the condition selected by the  
BRKSEL pin.  
tOFF should be in the range between 10 µs and 50 µs. Larger  
values for tOFF could result in audible noise problems. For  
proper circuit operation, 10 k< RT < 500 k.  
Power Loss Brake. The BRKCAP and BRKSEL pins  
provide a power-down braking option. A Power-Loss Brake  
Trigger Event, which is either an undervoltage on VREG  
or a RESET = 1 rising edge, is sensed by the A3938, which  
then dynamically brakes or coasts (depending on the stored  
BRKSEL setting) the motor. The reservoir capacitor on the  
BRKCAP pin provides the positive voltage that forces the  
low-side gates of the power MOSFETs high, keeping them  
on, even after supply voltage is lost. A stored setting of BRK-  
SEL = 1 brakes the motor, but a stored setting of BRKSEL = 0  
coasts it. The combined effect of these settings is shown in the  
table Brake Control.  
Torque control can be implemented by varying the REF input  
voltage as long as the PWM input stays high. If direct control  
of the torque/current is desired by PWM input, a voltage can  
be applied to the REF pin to set an absolute maximum cur-  
rent limit.  
PWM Blank. The capacitor CT also serves as the means  
to set the BLANK time duration. At the end of a PWM  
off-cycle, a high-side gate selected by the commutation logic  
turns on. At this time, large current transients can occur dur-  
ing the reverse recovery time, trr, of the intrinsic body diodes  
Brake Control  
BRAKE BRKSEL  
Before Power Loss Brake Trigger Event  
After Power Loss Brake Trigger Event  
Coast mode – All gate drive outputs OFF  
Brake mode – All low-side gate drivers ON  
0
0
1
1
0
1
0
1
Normal run mode  
Normal run mode  
Brake mode – All low-side gate drivers ON Coast mode – All gate drive outputs OFF  
Brake mode – All low-side gate drivers ON Brake mode – All low-side gate drivers ON  
8
www.allegromicro.com  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  

A3938SLD 替代型号

型号 品牌 替代类型 描述 数据表
A3932SLDTR-T ALLEGRO

完全替代

暂无描述
A3938SLDTR-T ALLEGRO

完全替代

暂无描述
A3932SLD-T ALLEGRO

完全替代

Three-Phase Power MOSFET Controller

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