Datasheet > A32400DX-1PQG240I

A32400DX-1PQG240I

更新时间： 2024-02-08 07:58:19

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
22页	207K
描述
Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240

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A32400DX-1PQG240I 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-240	Reach Compliance Code：	compliant
风险等级：	5.84	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G240	JESD-609代码：	e3
长度：	32 mm	湿度敏感等级：	3
可配置逻辑块数量：	2526	等效关口数量：	40000
端子数量：	240	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2526 CLBS, 40000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	245	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	32 mm
Base Number Matches：	1

A32400DX-1PQG240I 数据手册

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3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y

analogous to the wide-input AND term in a CPLD or PAL

device. The output of the D-module has a programmable

inverter for active HIGH or LOW assertion. The D-module

output is hardwired to an output pin or can be fed back into

the array to be incorporated into other logic.

7 inputs

Du a l-P o r t S R AM Mo d u le s

hardwire to I/O

The 3200DX dual-port SRAM modules have been optimized

for synchronous or asynchronous applications. The SRAM

modules are arranged in 256 bit blocks which can be

configured as 32 x 8 or 64 x 4 (refer to Table 1 for the number

of SRAM modules within a particular device). The SRAM

module block structure allows them to be cascaded together

to form user-definable memory spaces. Resources within the

3200DX architecture allow the SRAM modules to be

cascaded together without incurring an additional delay

penalty. A block diagram of the 3200DX dual-port SRAM

block is shown in Figure 4.

Programmable

inverter

feedback to array

Figure 3 • D-Module Implementation

and read ports of the SRAM block have eight data inputs

(WD[7:0]) and eight outputs (RD[7:0]). The SRAM block

outputs are connected to segmented vertical routing tracks.

The 3200DX SRAM blocks are true dual-port structures

containing independent READ and WRITE logic. The

SRAM blocks contain six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0] respectively) for 64x4 bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM blocks contain independent

clocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The write

The 3200DX dual-port SRAM blocks are ideal for

high-speed buffered applications such as DMA controllers

and FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory elements,

such as FIFOs, LIFOs, and RAM arrays which can be

included in any 3200DX design. Additionally, unused SRAM

blocks can be used to implement registers for other logic

within the design.

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 bits)

WRAD[5:0]

[5:0]

LEN

REN

Read

Logic

Latches

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 4 • Dual-Port SRAM Module

1 2 3 456 7 8...22

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与A32400DX-1PQG240I相关器件

型号	品牌	描述	获取价格	数据表
A32400DX-1RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-1RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2BGG313I	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PBGA313, BGA-313	获取价格
A32400DX-2PQG240C	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240	获取价格
A32400DX-2RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格

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