3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
P i n D e s c r i p t i o n
Q C LK A/B , C , D Q u a d r a n t C lo c k (In p u t /O u t p u t )
These four pins are the quadrant clock inputs. When not used
as a register control signal, these pins can function as general
purpose I/O.
C LK A, C LK B C lo c k A a n d C lo c k B (in p u t )
TTL Clock inputs for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
S DI
S e r ia l Da t a In p u t (In p u t )
DC LK
Dia g n o s t ic C lo c k (In p u t )
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
T C K
T e s t C lo c k
G N D
G r o u n d (In p u t )
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
Input LOW supply voltage.
I/O
In p u t /O u t p u t (In p u t , O u t p u t )
T DI
T e s t Da t a In
I/O pin functions as an input, output, three-state or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as
an I/O when the JTAG fuse is not programmed.
T DO
T e s t Da t a O u t
MO DE
Mo d e (In p u t )
Serial data output for JTAG instructions and test data. This
pin functions as an I/O when the JTAG fuse is not
programmed.
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is
HIGH, the special functions are active.
T MS
T e s t Mo d e S e le c t
N C
N o C o n n e c t io n
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed.
This pin is not connected to circuitry within the device.
P R A/I/O
P r o b e A (O u t p u t )
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
V
S u p p ly Vo lt a g e (In p u t )
C C
Input HIGH supply voltage.
Note: TCK, TDI, TDO, TMS are only available on
devices containing JTAG circuitry.
3 2 0 0 D X A r c h i t e c t u r a l O v e r v i e w
The 3200DX family architecture is composed of fine-grained
building blocks which produce fast, efficient logic designs.
All devices within the 3200DX family are composed of
Logic Modules, Routing Resources, Clock Networks, and I/O
modules which are the building blocks to design fast logic
designs. In addition, a subset of the device family contains
embedded dual-port SRAM modules which can implement
fast SRAM functions such as FIFOs, LIFOs, and scratchpad
memory.
P R B /I/O
P r o b e B (O u t p u t )
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
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