Datasheet > A32400DX-1PQG240I

A32400DX-1PQG240I

更新时间： 2024-01-30 15:51:57

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
22页	207K
描述
Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240

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A32400DX-1PQG240I 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-240	Reach Compliance Code：	compliant
风险等级：	5.84	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G240	JESD-609代码：	e3
长度：	32 mm	湿度敏感等级：	3
可配置逻辑块数量：	2526	等效关口数量：	40000
端子数量：	240	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2526 CLBS, 40000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	245	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	32 mm
Base Number Matches：	1

A32400DX-1PQG240I 数据手册

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3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y

C lo c k N e t w o r k s

Two low-skew, high fanout clock distribution networks are

provided in each 3200DX device. These networks are

referred to as CLK0 and CLK1. Each network has a clock

module (CLKMOD) that selects the source of the clock

signal and may be driven as follows:

CLKB

CLKA

CLKINB

CLKINA

FROM

PADS

INTERNAL

SIGNAL

CLKMOD

1. Externally from the CLKA pad

2. Externally from the CLKB pad

3. Internally from the CLKINA input

4. Internally from the CLKINB input

CLKO(17)

CLKO(16)

CLKO(15)

CLOCK

DRIVERS

The clock modules are located in the top row of I/O modules.

Clock drivers and a dedicated horizontal clock track are

located in each horizontal routing channel.

The user controls the clock module by selecting one of two

clock macros from the macro library. The macro CLKBUF is

used to connect one of the two external clock pins to a clock

network, and the macro CLKINT is used to connect an

internally generated clock signal to a clock network. Since

both clock networks are identical, the user does not care

whether CLK0 or CLK1 is being used. The clock input pads

may also be used as normal I/Os, bypassing the clock

networks (see Figure 7).

CLKO(2)

CLKO(1)

CLOCK TRACKS

Figure 7 • Clock Networks

The 3200DX devices which contain SRAM modules (all

except A3265DX and A32140DX) have four additional

(Figure 8). Each quadrant clock provides a local, high-fanout

resource to the contiguous logic modules within its quadrant

of the device. Quadrant clock signals can originate from

specific I/O pins or from the internal array and can be used as

a secondary register clock, register clear, or output enable.

T e s t C ir c u it r y

The 3200DX provides two modes of device and/or

board-level testing; JTAG 1149.1 Boundary Scan Testing

and Actel’s Actionprobe® test facility. Once a 3200DX

device has been programmed, the Actionprobe test facility

QCLKA

QCLKC

Quad

Clock

Module

Clock

Module

QCLK1

QCLK3

QCLKB

QCLKD

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Quad

Clock

QCLK2

QCLK4

Module

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

*QCLK1IN, QCLK2IN, QCLK3IN, and QCKL4IN are internally generated signals.

Figure 8 • Quadrant Clock Network

1...4 5 678 9 10...22

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与A32400DX-1PQG240I相关器件

型号	品牌	描述	获取价格	数据表
A32400DX-1RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-1RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2BGG313I	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PBGA313, BGA-313	获取价格
A32400DX-2PQG240C	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240	获取价格
A32400DX-2RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格

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